中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

79 records (took 0.02 seconds)

    Sigma-delta modulators with high speed feed-forward architecture
    31.
    发明授权
    Sigma-delta modulators with high speed feed-forward architecture 有权
    具有高速前馈架构的Σ-Δ调制器

    公开(公告)号：US09019136B2

    公开(公告)日：2015-04-28

    申请号：US14097451

    申请日：2013-12-05

    Applicant: MediaTek Inc.

    Inventor： Chen-Yen Ho ,  Hung-Chieh Tsai ,  Yu-Hsin Lin

    IPC: H03M3/00 ,  H03M1/00 ,  H03M1/12

    CPC classification number: H03M3/32 ,  H03M1/00 ,  H03M1/12 ,  H03M3/30 ,  H03M3/452 ,  H03M2201/4233

    Abstract: A sigma-delta modulator is provided for generating a digital output signal. The sigma-delta modulator is used to generate a digital output signal. The sigma-delta modulator includes a multi-stage loop filter and a quantizer. The multi-stage loop filter receives an analog input signal and generates an integrated output signal according to the analog input signal. The quantizer is coupled to the multi-stage loop filter. The quantizer receives the integrated output signal and quantizes the integrated output signal to generate the digital output signal. Different feed-forward paths of the sigma-delta modulator are available for different frequency bands.

    Abstract translation: 提供Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器用于产生数字输出信号。 Σ-Δ调制器包括多级环路滤波器和量化器。 多级环路滤波器接收模拟输入信号，并根据模拟输入信号产生积分输出信号。 量化器耦合到多级环路滤波器。 量化器接收积分输出信号并量化积分输出信号以产生数字输出信号。 Σ-Δ调制器的不同前馈路径可用于不同的频带。

    Time-to-digital converter
    32.
    发明授权
    Time-to-digital converter 有权
    时间到数字转换器

    公开(公告)号：US08896477B2

    公开(公告)日：2014-11-25

    申请号：US14265148

    申请日：2014-04-29

    Applicant: Panasonic Corporation

    Inventor： Shiro Dosho ,  Masao Takayama

    IPC: H03M1/50 ,  G04F10/00 ,  H03M1/18 ,  H03M1/12 ,  H03L7/087 ,  H03M1/00 ,  H03L7/081 ,  H03L7/18

    CPC classification number: G04F10/005 ,  H03L7/0814 ,  H03L7/087 ,  H03L7/18 ,  H03M1/00 ,  H03M1/12 ,  H03M1/18 ,  H03M2201/4233

    Abstract: An edge detector includes flip-flops receiving phase signals of a ring oscillator, a resetter canceling the reset states of the flip-flops at the edge timing of an input signal, and a logical operator performing a logical operation on output signals of the flip-flops. A phase state detector detects a phase state of the ring oscillator occurring at the edge timing of the input signal based on the output signals of the flip-flops. A time-to-digital converter converts an edge interval between the input signal and an output signal of the logical operator into a digital value. A latch latches a value of a counter counting the number of cycles of an output signal of the ring oscillator, at the edge timing of the input signal. An operator calculates a digital value of a received signal from output signals of the latch, the phase state detector, and the time-to-digital converter.

    Abstract translation: 边沿检测器包括接收环形振荡器的相位信号的触发器，在输入信号的边缘定时取消触发器的复位状态的复位器，以及对触发器的输出信号执行逻辑运算的逻辑运算器， 翻牌 相位状态检测器基于触发器的输出信号来检测在输入信号的边缘定时处发生的环形振荡器的相位状态。 时间 - 数字转换器将输入信号和逻辑运算器的输出信号之间的边沿间隔转换为数字值。 在输入信号的边缘定时处，锁存器锁存计数环形振荡器的输出信号的周期数的计数器的值。 操作者根据锁存器，相位状态检测器和时间 - 数字转换器的输出信号计算接收信号的数字值。

    Analogue-to-digital converter
    33.
    发明授权
    Analogue-to-digital converter 有权
    模数转换器

    公开(公告)号：US08742970B2

    公开(公告)日：2014-06-03

    申请号：US13902638

    申请日：2013-05-24

    Applicant: Wolfson Microelectronics plc

    Inventor： John Paul Lesso ,  John Laurence Pennock

    IPC: H03M1/60 ,  H03M1/00 ,  H03M1/12

    CPC classification number: H03M1/00 ,  H03M1/1014 ,  H03M1/12 ,  H03M1/1225 ,  H03M1/186 ,  H03M1/34 ,  H03M1/60 ,  H03M2201/4233

    Abstract: An apparatus and method for regulating analogue-to-digital converters. First and second input signals are received at controlled oscillator circuitry which generates respective first and second pulse streams with pulse rates based on the relevant input signal. Difference circuitry determines the difference in number of pulses of the first and second pulse streams and outputs a first digital signal. Circuitry also determines a signal independent value based on the number of pulses of the first and/or second pulse streams. In one embodiment this value is the sum or average of the number of pulses of the first and second pulse streams. This value can be used to calibrate for any variation in transfer characteristic of the oscillator circuitry. In one embodiment this value is compared to a reference value and a regulation signal passed to control circuitry to regulate the operation of the oscillation circuitry.

    Abstract translation: 一种用于调节模数转换器的装置和方法。 在受控振荡器电路处接收第一和第二输入信号，该电路产生具有基于相关输入信号的脉冲速率的相应的第一和第二脉冲流。 差分电路确定第一和第二脉冲流的脉冲数的差异并输出第一数字信号。 电路还基于第一和/或第二脉冲流的脉冲数来确定与信号无关的值。 在一个实施例中，该值是第一和第二脉冲流的脉冲数的和或平均值。 该值可用于校准振荡器电路的传输特性的任何变化。 在一个实施例中，该值与参考值和传递给控制电路的调节信号进行比较以调节振荡电路的操作。

    Comparison circuits
    34.
    发明授权
    Comparison circuits 有权

    公开(公告)号：US08514121B1

    公开(公告)日：2013-08-20

    申请号：US13430464

    申请日：2012-03-26

    Applicant: Yun-Shiang Shu

    Inventor： Yun-Shiang Shu

    IPC: H03M1/12

    CPC classification number: H03M1/50 ,  H03M1/00 ,  H03M1/12 ,  H03M1/206 ,  H03M1/365 ,  H03M2201/4233

    Abstract: A comparison circuit is provided and includes first and second comparators and a first time-to-digital comparator. The first comparator with a first offset voltage receives an input signal and generates a first comparison signal and a first inverse comparison signal. The second comparator receives the input signal and generates a second comparison signal and a second inverse comparison signal. The first offset voltage is larger than the second offset voltage. The first time-to-digital comparator receives the first comparison signal and the second inverse comparison signal and generates first and second determination signals according to the first comparison signal and the second inverse comparison signal. The first and second determination signals indicate whether a voltage of the input signal is larger than a first middle voltage. The first middle voltage is equal to a half of the sum of the first offset voltage and the second offset voltage.

    Method and system for translating digital signal sampled at variable frequency
    35.
    发明授权
    Method and system for translating digital signal sampled at variable frequency 失效
    用于转换可变频率采样的数字信号的方法和系统

    公开(公告)号：US4568912A

    公开(公告)日：1986-02-04

    申请号：US475406

    申请日：1983-03-15

    Applicant: Masatsugu Kitamura ,  Mitsuaki Tanaka

    Inventor： Masatsugu Kitamura ,  Mitsuaki Tanaka

    IPC: H03M1/00 ,  H04B12/02

    CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/162 ,  H03M2201/196 ,  H03M2201/198 ,  H03M2201/3115 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/415 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/532 ,  H03M2201/534 ,  H03M2201/648 ,  H03M2201/838

    Abstract: In a data compression system, a digital signal comprising a series of digital samples and a sampling datum associated with each digital sample is received by a decoder. The sampling datum indicates the sampling interval of the associated digital sample. The decoder includes a microcomputer for storing the digital signal into a memory (M2) and reading each digital sample and the associated sampling datum. The digital sample is divided by the sampling datum to derive a quotient which indicates the slope of the signal to be recovered. The quotient is integrated by an integrator (6b) to provide interpolation between successive sampling points, so that the original signal is approximated by a plurality of line segments.

    Abstract translation: 在数据压缩系统中，由解码器接收包括一系列数字样本和与每个数字样本相关联的采样数据的数字信号。 采样数据表示相关数字采样的采样间隔。 解码器包括用于将数字信号存储到存储器（M2）中并读取每个数字样本和相关联的采样数据的微型计算机。 数字样本被采样数据除以导出指示要恢复的信号的斜率的商。 积分器（6b）对商进行积分，以在连续采样点之间提供内插，使原始信号由多个线段近似。

    Multi stage resistive ladder network having extra stages for trimming
    37.
    发明授权
    Multi stage resistive ladder network having extra stages for trimming 失效
    多级电阻梯形网络具有额外的修整阶段

    公开(公告)号：US4338590A

    公开(公告)日：1982-07-06

    申请号：US110135

    申请日：1980-01-07

    Applicant: Joseph J. Connolly, Jr. ,  James B. Cecil

    Inventor： Joseph J. Connolly, Jr. ,  James B. Cecil

    IPC: H03M1/00 ,  H03K13/02

    CPC classification number: H03M1/00 ,  H03M2201/02 ,  H03M2201/3115 ,  H03M2201/3131 ,  H03M2201/3136 ,  H03M2201/3168 ,  H03M2201/4135 ,  H03M2201/4225 ,  H03M2201/4233 ,  H03M2201/4262 ,  H03M2201/6121 ,  H03M2201/63 ,  H03M2201/814

    Abstract: A multi-stage resistive ladder network which uses extra stages to trim out resistance discrepencies. All of the stages are interconnected in a series. Nominally, current is divided in half within each stage. Half of the current is gated onto a bus in response to logic control signals, and the other half of the current is passed onto the next succeeding stage. Due to various processing limitations, the resistors comprising each stage vary slightly from their nominal value, which in turn upsets the current division. To compensate for this additional current dividing stages are serially connected to the last stage of the ladder. Current from these additional stages are selectively coupled onto the bus in response to the logic signals in addition to the current which is normally coupled thereto.

    Abstract translation: 一个多级电阻梯形网络，使用额外的级来修剪阻抗差异。 所有的阶段都是相互联系的。 名义上，目前在每个阶段都分成两半。 响应于逻辑控制信号，一半的电流被门控在总线上，而另一半的电流被传递到下一个后续阶段。 由于各种处理限制，包括每个级的电阻器与它们的标称值略有不同，这反过来扰乱了当前的划分。 为了补偿这个额外的电流分级级与梯子的最后阶段串联连接。 来自这些附加级的电流除了通常耦合到其上的电流之外还响应于逻辑信号而选择性地耦合到总线上。

Patent Agency Ranking