Abstract:
PURPOSE: A method for manufacturing an FET(Field Effect Transistor) having an LDD(Lightly Doped Drain) is provided to be capable of improving the reproductivity of a process, automating the process, and preventing contamination. CONSTITUTION: After forming the first oxide layer at the upper portion of an isolating layer, the first oxide sidewalls(45a,45b) are formed at both sides of a gate(43a) by carrying out the first dry etching process at the first oxide layer. After forming a nitride layer at the upper portion of the resultant structure, nitride sidewalls are formed at each outer portion of the first oxide sidewalls by carrying out the second dry etching process at the nitride layer. Then, a source and drain region(48a,48b) are formed at a semiconductor substrate(41) by implanting ions. The nitride sidewalls are removed by carrying out the third dry etching process for remaining the first oxide sidewalls alone. At this time, the insulating layer is selectively etched.
Abstract:
A single electron transistor including a constriction barrier and a manufacturing method thereof are provided to implement a tunneling barrier by forming a constriction barrier in an active region in both sides of a control gate. A channel region(12a) is defined as the predetermined micro pattern in a silicon layer(10) of an SOI substrate. A source region(24) and a drain region(26) are separated with a predetermined distance while interposing a channel region. A gate insulating layer is formed in the upper part of the channel region. The gate is formed in the upper part of the gate insulating layer. A channel constriction oxide layer(72) is self-aligned in both sides of the gate. The channel constriction oxide layer encroaches on the channel region.
Abstract:
A FIREFET(Fin and Recess channel MOSFET) and a manufacturing method thereof are provided to improve a current driving performance of the FIREFET by reducing source and drain resistances. An active region is surrounded by a field oxide film on a semiconductor substrate. Source/drain(14,16) are formed on the active region with a fin-type channel between them. A recess hole is formed under the source/drain and the fin channel. A recess channel is formed under the fin channel at one side of the recess hole. Gate oxide films(80) are formed on a surface of the recess hole including the recess channel, side surfaces of the source/drain, and the fin channel. A gate(90a) surrounds the recess channel and the fin channel on the gate oxide film and is formed between the recess hole and the source/drain.
Abstract:
A semiconductor probe using an impact-ionization semiconductor device is provided to remarkably improve the limit of sensitivity of a resistive probe and easily adjust the quantity of charges capable of being detected by a probe by developing a new probe structure for easily adjusting the band energy of a source. One tilted surface of a probe is formed by an anisotropic etch process using a first etch mask pattern formed on a silicon substrate. After impurities are doped into the exposed substrate to form a first semiconductor electrode region(16), the first etch mask pattern is removed. A second etch mask pattern opposite to the direction of the first etch mask pattern is formed on the silicon substrate. Space layers are formed on the sidewalls of the second etch mask pattern. After the exposed silicon substrate is anisotropically etched to form an opposite tilted surface of the probe, the second etch mask pattern is removed. Impurities are doped into the exposed substrate to form a second semiconductor electrode region(18), and the second etch mask pattern is removed. A silicon oxide layer pattern is formed on the resultant structure by a known method. Space layers are formed on both sidewalls of the silicon oxide layer pattern. By using the space layer, a predetermined depth of the silicon substrate is etched by a photolithography process, and the space layer is removed. The first semiconductor electrode region can be a source terminal, and the second semiconductor electrode region can be a drain terminal.
Abstract:
본 발명은 산화막인 게이트 절연막 위에 PMMA 층 또는 증가형 특성을 보이는 게이트 절연막을 도입하여 제조한 p 채널 증가형 소자 및 p 채널 공핍형 소자를 연결하거나, 게이트 절연막으로서 비휘발성 유기 메모리 층을 도입하고 전기적인 프로그래밍에 의하여 음의 문턱전압을 갖는 p 채널 증가형 소자 및 전기적인 프로그래밍에 의하여 양의 문턱전압을 갖는 p 채널 공핍형 소자를 연결한 유기 반도체 회로가 제공된다. 본 발명의 p 채널 증가형 소자와 p 채널 공핍형 소자를 함께 동일 기판 위에 형성하고, 연결하면 풀 스윙이 가능한 반도체 회로를 쉽게 구현할 수 있다. p 채널, 유기 반도체 회로, 풀 스윙, 증가형 소자, 공핍형 소자, PMMA 층, 게이트 절연막, 유기 메모리, 프로그래밍
Abstract:
본 발명은 메사(mesa) 구조를 가진 터널링 소자에 관한 것으로, 계단 형상의 반도체기판과; 상기 반도체기판의 돌출된 일단에 형성된 드레인 영역과; 상기 드레인 영역 상부에 형성된 마스크층과; 상기 드레인 영역의 일측면과 상기 반도체기판의 타단 상부 전면에 형성된 게이트 절연막과; 상기 게이트 절연막 상부 꺾인 부위에 형성된 측벽 게이트와; 상기 측벽 게이트의 가장자리에 맞추어 상기 반도체기판의 타단 일면적 밑에 형성된 소스 영역으로 구성된 터널링 전계효과 트랜지스터의 구조를 제공하여, 본 발명에 의한 측벽 게이트와 절연막 측벽들을 적절히 이용하게 되면 종래 MOSFET 구조의 터널링 소자 제조공정에서 소요되는 마스크 수를 대폭 줄여 공정 단가를 낮출 수 있는 효과가 있다. 터널링, 반도체, 소자, 자기 정렬
Abstract:
본 발명은 이온화 충돌을 이용한 반도체 소자 및 그 제조방법에 관한 것으로, 본 발명에 따른 반도체 소자는 계단 형상의 반도체기판과; 상기 반도체기판의 돌출된 일단에 형성된 소스 영역과; 상기 소스 영역 상부에 형성된 마스크층과; 상기 소스 영역의 일측면과 상기 반도체기판의 타단 상부 전면에 형성된 게이트 절연막과; 상기 게이트 절연막 상부 꺾인 부위에 형성된 측벽 게이트와; 상기 반도체기판의 타단에 일정 길이의 진성영역을 구현하기 위해 상기 측벽 게이트 및 상기 게이트 절연막의 상부에 형성된 제 1 절연막 측벽과; 상기 제 1 절연막 측벽의 가장자리에 맞추어 상기 반도체기판의 타단 일면적 밑에 형성된 드레인 영역으로 구성된 것으로서, 종래의 반도체 소자와 달리 소스 또는 드레인 중 어느 하나의 영역이 돌출되고 측벽 게이트를 이용하기 때문에 제조공정을 간단히 할 수 있으며, 게이트, 소스/드레인, 채널 및 진성영역이 자기 정렬되어 형성되며, 기생성분이 억제되어 소자의 성능을 향상시킬 수 있고, 궁극적으로는 소자의 축소화가 용이한 장점이 있다.
Abstract:
PURPOSE: A single electron transistor is provided to control the size of a quantum dot by forming the first gate on the sidewall of a channel and by adjusting the height of the first gate left on the sidewall of the channel in etching the first gate material. CONSTITUTION: An insulator is formed on a substrate support unit. Source and drain regions are formed of single crystalline silicon, separated from each other on the insulator. A channel formed of single crystalline silicon is formed on the insulator, connected to the source region and the drain region. The first insulation layer is deposited on the channel and a part of the source and drain regions in a straight line with the channel. The first gate insulation layer(36) is deposited on both sidewalls of the channel and on the sidewall of the source and drain regions. The first gate(37) is formed on a part of both sidewalls of the channel over the first gate insulation layer and on the sidewall of the source and drain. The second gate insulation layer(38) is deposited on the first gate and a part of both sidewalls of the channel wherein the first gate is not formed. The second gate(39) surrounds the channel over the second gate insulation layer and the first insulation layer, formed between the source and drain regions.
Abstract:
PURPOSE: A method for forming ultra-fine multi-patterns is provided to obtain the ultra-fine multi-patterns of a desired size in a narrow interval by performing a multiple patterning process using a sidewall. CONSTITUTION: A pattern layer, the second pattern layer, and the first pattern layer are sequentially deposited on a substrate. The first pattern is formed on the first pattern layer. The first sidewall layer is deposited on the first pattern. A sidewall is formed by performing a dry etch process. The second pattern is formed by etching the second pattern layer. The sidewall is removed from the second pattern. The second sidewall layer is deposited on the second pattern. The second sidewall(22') is formed by performing the dry etch process. A pattern(P) is formed by etching the pattern layer.
Abstract:
PURPOSE: A metal oxide semiconductor field effect transistor(MOSFET) with a dual gate is provided to reduce contact resistance between polycrystalline silicon and a pin, by using a monocrystalline silicon portion on a buried oxide layer of a silicon-on-insulator(SOI) substrate. CONSTITUTION: An insulator is formed on a semiconductor substrate(10). A source region and a drain region are formed on the insulator, composed of monocrystalline silicon and separated from each other while an area lies between the source region and the drain region. A channel formed of monocrystalline silicon is formed on the insulator, crossing a part of the area and connecting the source region with the drain region. An insulation layer is formed on the channel. A gate is formed on the area between the source region and the drain region, surrounding the channel, both side surfaces of the insulation layer and the upper portion of the insulation layer. A gate insulation layer(15,15') is formed between the gate and the source/drain region to make the gate independent of the source/drain region electrically.