公开(公告)号：DE60304209D1

公开(公告)日：2006-05-11

申请号：DE60304209

申请日：2003-10-28

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： DEBROSSE JOHN ,  GOGL DIETMAR ,  HOENIGSCHMID HEINZ

IPC: G11C11/16 ,  G11C11/15 ,  H01L21/8246 ,  H01L27/22

Abstract: A memory device includes a magnetic tunnel junction memory cell having a magnetic tunnel junction structure and a read switch. In one example, the read switch is connected to a conductor that is used to write to the magnetic tunnel junction structure. In a further example, the read switch is a transistor electrically coupled to the magnetic tunnel junction structure by a deep via contact. In a further example, the memory device includes a plurality of magnetic tunnel junction memory cells and a plurality of conductors respectively associated with the cells for writing information to the associated magnetic tunnel junction structures. Each read switch is connected to the conductor associated with a magnetic tunnel junction cell other than the cell in which the read switch resides.

公开(公告)号：DE10058782B4

公开(公告)日：2006-03-23

申请号：DE10058782

申请日：2000-11-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ

IPC: H01L21/8239 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/11507

Abstract: In order to provide a particularly space-saving capacitor configuration in a memory device, a plurality of second electrode regions which are not in direct electrical contact with one another are formed on areas of a first electrode region covered by a dielectric material. During operation of the capacitor configuration, portions of the first electrode region form bottom electrodes which are connected by a connecting region, so that an additional connecting device for the bottom electrodes is not necessary.

公开(公告)号：DE10017368B4

公开(公告)日：2005-12-15

申请号：DE10017368

申请日：2000-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  ESTERL ROBERT ,  HOENIGSCHMID HEINZ ,  KANDOLF HELMUT

IPC: G11C11/22 ,  G11C7/02 ,  G11C7/08 ,  G11C7/22

Abstract: A description is given of a method for operating an integrated memory which has memory cells each having a selection transistor and a storage capacitor with a ferroelectric storage effect. The memory contains a plate line, which is connected to one of the column lines via a series circuit containing a selection transistor and a storage capacitor of respective memory cells. A memory access is carried out according to the "pulsed plate concept". In this case, the temporal sequence is controlled in such a way that, in an access cycle, the storage capacitor of the memory cell to be selected is in each case charged and discharged by the same amount. An attenuation or destruction of the information stored in the memory cells, which is caused by source-drain leakage currents of unactivated selection transistors, is thus avoided.

公开(公告)号：DE69828547D1

公开(公告)日：2005-02-17

申请号：DE69828547

申请日：1998-06-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: H01L27/108 ,  G11C7/12 ,  G11C11/4094 ,  H01L21/8242 ,  G11C11/409 ,  G11C7/00

Abstract: An equalizer circuit for precharging a pair of bit lines in a dynamic random access memory circuit. The equalizer circuit includes a substantially T-shaped polysilicon gate portion oriented at an angle relative to the pair of bit lines. The angle is an angle other than an integer multiple of 90 DEG . The substantially T-shaped polysilicon gate portion includes first polysilicon area for implementing a gate of a first switch of the equalizer circuit. The first switch is coupled to a first bit line of the pair of bit lines and a second bit line of the pair of bit lines. The substantially T-shaped polysilicon gate portion also includes a second polysilicon area for implementing a gate of a second switch of the equalizer circuit. The second switch is coupled to the first bit line of the pair of bit lines and a precharge voltage source. The substantially T-shaped polysilicon gate portion further includes a third polysilicon area for implementing a gate of a third switch of the equalizer circuit. The third switch is coupled to the second bit line of the pair of bit lines and the precharge voltage source.

公开(公告)号：DE19924567C2

公开(公告)日：2003-04-30

申请号：DE19924567

申请日：1999-05-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHLAGER TOBIAS ,  HOENIGSCHMID HEINZ

IPC: G11C5/02 ,  G11C11/22 ,  G11C11/405 ,  G11C7/00

Abstract: An integrated memory includes word lines and bit lines intersecting each other at crossover points. The bit lines are combined into bit line pairs and the bit line pairs are interleaved by having at least one of the bit lines of one bit line pair disposed between the two bit lines of another bit line pair. 2-transistor/2-capacitor memory cells each have two 1-transistor/1-capacitor memory cells each disposed at a respective one of the crossover points. Each of the two 1-transistor/1-capacitor memory cells of the 2-transistor/2capacitor memory cells have a selection transistor connected to one of the two bit lines of a respective one of the bit line pairs and to at least one of the word lines. The selection transistors may be simultaneously activated for simultaneously accessing the two 1-transistor/1-capacitor memory cells of one of the 2-transistor/2-capacitor memory cell.

公开(公告)号：DE10123593C2

公开(公告)日：2003-03-27

申请号：DE10123593

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22 ,  G11C11/14

Abstract: A magnetic memory configuration stores data and avoids ageing effects. The memory configuration contains a cell array containing magnetic memory cells disposed along a first direction and a second direction crossing the former, a multiplicity of electrical lines along the first direction, and a multiplicity of electrical lines along the second direction. The magnetic memory cells in each case are disposed at crossover points of the electrical lines. A first current supply device supplies respectively selected electrical lines along the first direction with current. A second current supply device supplies respectively selected electrical lines along the second direction with current. The second current supply device is configured for setting the direction of the current in accordance with an information item to be written. The first current supply device is suitable for changing over the direction of the current as desired.

公开(公告)号：DE59904238D1

公开(公告)日：2003-03-13

申请号：DE59904238

申请日：1999-07-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  MANYOKI ZOLTAN ,  BOEHM THOMAS ,  NEUHOLD ERNST ,  BRAUN GEORG

IPC: G11C11/407 ,  G11C5/14 ,  G11C8/00 ,  G11C8/08 ,  G11C16/12 ,  H03K19/094 ,  H03K19/20 ,  H03M5/16 ,  H03M7/00

Abstract: A decoder element is provided with an output, whereby an output signal with one of three different possible potentials is produced. The output signal may have a value of either a first potential, a second potential, and a third potential, where the second potential lies between the first potential and the third potential. The output signal is produced according to voltage values of input signals at terminal connections of the decoder element.

公开(公告)号：DE10123593A1

公开(公告)日：2002-11-28

申请号：DE10123593

申请日：2001-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ ,  KANDOLF HELMUT ,  LAMMERS STEFAN

IPC: G11C11/15 ,  G11C11/16 ,  H01L21/8246 ,  H01L27/105 ,  H01L43/08 ,  H01L27/22

Abstract: The arrangement has a field of magnetic memory cells along two mutually perpendicular directions, electrical conductors along both directions with memory cells at the intersection points, first and second current supplies for selectively supplying leads in the first and second directions respectively, whereby the second supply device sets the current direction according to information to be written. The first device changes the current direction. The arrangement has a cell field of magnetic memory cells arranged along first and second mutually perpendicular directions, electrical conductors (3a-3d;4a-4d) along both directions with magnetic memory cells (5aa-5dd) at the intersection points of the conductors, first and second current supplies (6,7) for selectively supplying leads in the first and second directions respectively, whereby the second supply device sets the current direction according to information to be written. The first current supply device changes the direction of the current. AN Independent claim is also included for the following: a magnetic memory cell.

公开(公告)号：DE19844402C2

公开(公告)日：2002-11-14

申请号：DE19844402

申请日：1998-09-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRAUN GEORG ,  MAZURE-ESPEJO CARLOS ,  HOENIGSCHMID HEINZ ,  MAJDIC ANDREJ

IPC: G11C11/22 ,  G11C7/00

Abstract: An integrated memory device or store includes write-to memory cells (MC), a first differential read-amplifier (SA;SSA) with terminals connected to a data line pair (BLL;DL) allowing relevant information to be passed over the data lines as difference signals and temporarily stored at each write-access. A switch unit (SW) connects the data lines (BLL;DL) to the first read amplifier (SA;SSA) and reverse the terminals of the data lines to the read-amplifier depending on the switching state, where the latter changes at least once during a write-access so that the write-in information from the first amplifier (SA;SSA) is initially non-inverted and then inverted in the relevant memory cell (MC).

公开(公告)号：DE10059181C2

公开(公告)日：2002-10-24

申请号：DE10059181

申请日：2000-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOENIGSCHMID HEINZ

IPC: H01L21/8246 ,  H01L27/22 ,  G11C11/15 ,  G11C11/14 ,  G11C11/16

Abstract: The integrated connecting conductors (10) having word lines (1), digit lines (3), bit lines (5) and isolation element activating line, are located in selected plane of any one of the metallization planes and a polysilicon connection plane. An independent claim is included for integrated magnetoresistive semiconductor memory fabrication method.