公开(公告)号：DE102008038170B4

公开(公告)日：2010-10-28

申请号：DE102008038170

申请日：2008-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STAPELMANN CHRIS ,  SCHULZ THOMAS

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/78

公开(公告)号：DE50312210D1

公开(公告)日：2010-01-21

申请号：DE50312210

申请日：2003-10-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BREDERLOW RALF ,  HARTWICH JESSICA ,  PACHA CHRISTIAN ,  ROESNER WOLFGANG ,  SCHULZ THOMAS

IPC: H01L27/12 ,  H01L21/8242 ,  H01L21/84 ,  H01L27/108

Abstract: An integrated circuit arrangement and method of fabricating the integrated circuit arrangement is described. The integrated circuit arrangement contains an insulating region and a sequence of regions which forms a capacitor. The sequence contains a near electrode region near the insulating region, a dielectric region, and a remote electrode region remote from the insulating region. The insulating region is part of an insulating layer arranged in a plane. The capacitor and an active component are arranged on the same side of the insulating layer and form a memory cell. The near electrode region and an active region of the component are arranged in a plane which lies parallel to the plane in which the insulating layer is arranged. A processor is also contained in the integrated circuit arrangement.

公开(公告)号：DE112006000241B4

公开(公告)日：2010-01-21

申请号：DE112006000241

申请日：2006-02-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS

IPC: H01L21/336

Abstract: A semiconductor device includes a source region, a drain region, and a fin that connects the source region to the drain region. A gate electrode having a substantially planar surface overlies the fin and is positioned between the drain region and the source region. A first set of spacers is positioned between a first sidewall of the gate electrode and the source region and between a second sidewall of the gate electrode and the drain region. A second set of spacers is positioned on at least a portion of a top surface of the source region and the drain region and alongside at least a portion of the first set of spacers. At least a portion of sidewalls of the second set of spacers contacts a portion of the first or second sidewall of the gate electrode.

公开(公告)号：DE59814274D1

公开(公告)日：2008-10-02

申请号：DE59814274

申请日：1998-11-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  AEUGLE THOMAS DR ,  ROESNER WOLFGANG DR ,  RISCH LOTHAR DR

IPC: H01L27/11 ,  G11C11/40 ,  H01L21/8244

Abstract: The cell arrangement includes at least six transistors per memory cell. Four of the transistors form a flip-flop and are arranged at corners of a square. The flip-flop is controlled by two of the transistors which are respectively arranged adjacent on diagonally opposite corners of the square. Memory cells adjacent along a word conductor can be arranged in such a way, that a first bit conductor and a second bit conductor of the adjacent memory cells coincide. The transistors are arranged preferably vertically and in semiconductor structures which are produced by a layer sequence. Two of the transistors with n-endowed channel areas, are preferably formed in two separate semiconductor structures.

公开(公告)号：DE102007054058A1

公开(公告)日：2008-05-29

申请号：DE102007054058

申请日：2007-11-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOSSNER HARALD ,  RUSS CHRISTIAN ,  SCHNEIDER JENS ,  SCHULZ THOMAS

IPC: H01L29/78 ,  H01L21/336

公开(公告)号：DE102006022126A1

公开(公告)日：2007-11-15

申请号：DE102006022126

申请日：2006-05-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOSSNER HARALD ,  SCHULZ THOMAS ,  RUSS CHRISTIAN ,  KNOBLINGER GERHARD

IPC: H01L21/332 ,  H01L21/336 ,  H01L23/62 ,  H01L29/74 ,  H01L29/78

Abstract: The method involves forming doped connection regions (502, 503) on and/or over a substrate. Body regions (504, 505) are formed between the doped connection regions. Two separate gate regions are formed on and/or over the body regions, and a portion of the body regions is doped by introducing dopant atoms. The introduction of the dopant atoms into the portion of the body regions is carried out through an intermediate region formed between the separate gate regions. Independent claims are also included for the following: (1) a drain extended MOS field-effect transistor comprising two doped connection regions (2) an electronic component arrangement comprising drain extended MOS field-effect transistors.

公开(公告)号：DE102006013721A1

公开(公告)日：2007-09-27

申请号：DE102006013721

申请日：2006-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ARNIM KLAUS VON ,  SCHULZ THOMAS ,  PACHA CHRISTIAN

IPC: H01L23/58 ,  G01K7/01 ,  H01L21/66 ,  H01L23/544 ,  H01L27/06

Abstract: The arrangement has an insulating layer (2) formed on a semiconductor substrate (1). An active semiconductor region (AA) is formed on the insulating layer. Source and drain regions of a multi-gate FET are formed in the active region. A diode doped region is formed in the active semiconductor region of a specific conductive type up to a surface of the insulating layer. A measuring diode is realized over a diode side with the source and drain regions and is bordered at a side by another insulating layer (4). An independent claim is also included for a method for temperature determination in a semiconductor circuit arrangement.

公开(公告)号：DE10213545B4

公开(公告)日：2006-06-08

申请号：DE10213545

申请日：2002-03-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  GOETTSCHE RALF ,  PACHA CHRISTIAN ,  STEINHOEGL WERNER

IPC: H01L21/336 ,  H01L27/08 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/786

公开(公告)号：DE10254158A1

公开(公告)日：2004-06-09

申请号：DE10254158

申请日：2002-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHULZ THOMAS ,  JENKNER MARTIN ,  LYKEN JOHANNES ,  THEWES ROLAND

IPC: G01N27/414 ,  G01N33/487 ,  G01N33/50 ,  C12M1/34 ,  G01N33/483

Abstract: Sensor system for detecting signals from biological cells (24) comprises a semiconductor substrate (SUB) with an upper surface (26) on which the cells are placed. The substrate contains a field effect transistor whose channel has a coupling component connecting it to a sensor surface (16). Sensor system for detecting signals from biological cells (24) comprises a semiconductor substrate (SUB) with an upper surface (26) on which the cells are placed. The substrate contains a field effect transistor whose channel has a coupling component connecting it to a sensor surface (16). The normal to the sensor surface is at an angle to the normal to the upper surface of the substrate. The coupling component allows the conductivity of the channel to be affected by signals from the cells, using capacitive coupling. An Independent claim is included for a method for detecting electrical signals from biological cells using the sensor system

公开(公告)号：DE10250829A1

公开(公告)日：2004-05-19

申请号：DE10250829

申请日：2002-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUYKEN R JOHANNES ,  SPECHT MICHAEL ,  LANDGRAF ERHARD ,  SCHULZ THOMAS ,  ROESNER WOLFGANG ,  GRAHAM ANDREW

IPC: G11C13/02 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  H01L27/28 ,  H01L29/788 ,  H01L29/792 ,  H01L51/00 ,  H01L51/30

Abstract: A nonvolatile memory cell, memory cell arrangement, and method for production of a nonvolatile memory cell is disclosed. The nonvolatile memory cell includes a vertical field-effect transistor (FET). The FET contains a nanoelement arranged as a channel region and an electrically insulating layer. The electrically insulating layer at least partially surrounds the nanoelement and acts as a charge storage layer and as a gate-insulating layer. The electrically insulating layer is arranged such that electrical charge carriers may be selectively introduced into or removed from the electrically insulating layer and the electrical conductivity characteristics of the nanoelement may be influenced by the electrical charge carriers introduced into the electrically insulating layer.