公开(公告)号：FR2987168B1

公开(公告)日：2016-11-25

申请号：FR1300612

申请日：2013-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGER RUDOLF ,  GRUBER HERMANN ,  LEHNERT WOLFGANG ,  RUHL GUENTHER ,  FOERG RAIMUND ,  MAUDER ANTON ,  SCHULZE HANS JOACHIM ,  KELLERMANN KARSTEN ,  SOMMER MICHAEL ,  ROTTMAIR CHRISTIAN ,  RUPP ROLAND

IPC: H01L21/71 ,  H01L21/20 ,  H01L21/48 ,  H01L23/14

公开(公告)号：DE50114463D1

公开(公告)日：2008-12-18

申请号：DE50114463

申请日：2001-09-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DIETRICH STEFAN DR ,  HEYNE PATRICK ,  MARX THILO ,  SCHOENIGER SABINE ,  SOMMER MICHAEL ,  HEIN THOMAS ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  SCHROEGMEIER PETER ,  WEIS CHRISTIAN

IPC: G01R31/28 ,  G11C29/00 ,  G06F11/22 ,  G11C11/401 ,  G11C11/407 ,  G11C29/34 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04

Abstract: Integrated circuits, in particular memory chips of the DDR SDRAM type, are tested in a parallel manner. In order to prevent the circuits from being driven relative to one another during a test operation, an input terminal that is already connected to a channel of an automatic test machine anyway is connected to a switching device, by which the output drivers can be turned off in a manner dependent on the control signal that can be fed in at the input terminal. The switching device preferably contains a demultiplexer and also a multiplexer. The demultiplexer can be driven by a test control signal that is additionally generated besides the test control signal. The input terminal is connected to a tester channel anyway during test operation, with the result that no additional external outlay arises.

公开(公告)号：DE102004029200B4

公开(公告)日：2006-10-19

申请号：DE102004029200

申请日：2004-06-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DICKMANN RORY ,  SOMMER MICHAEL

IPC: H01L21/60 ,  H01L23/50 ,  H01L23/58 ,  H05K1/16 ,  H05K3/46

Abstract: The invention relates a substrate for a package for an electronic circuit and methods for packaging an electronic circuit with a substrate. The substrate comprises at least one conduction region and an activation region arranged within the substrate. The activation region is generally in contact with the conduction region and is configured to change its electrical resistance when activation occurs.

公开(公告)号：DE10322544B3

公开(公告)日：2004-08-26

申请号：DE10322544

申请日：2003-05-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: G11C7/06 ,  G11C11/4091

Abstract: The data reading amplifier (50) has two switching circuits (51,52) containing FET's (N1a-N3b) all of same conduction type with low resistance connections to their drains. The amplifier is connected to a DRAM (Dynamic Random Access Memory) (10) with an array of storage cells (20A,B). There is an equalization switching circuit (30) and a two pole data bit conduction switch (40).

公开(公告)号：DE10233760A1

公开(公告)日：2004-02-19

申请号：DE10233760

申请日：2002-07-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H01L21/822 ,  H01L21/8244 ,  H01L27/06 ,  H01L27/11 ,  H01L27/105 ,  H01L21/8239

Abstract: A circuit structure has at least two etching trenches disposed at sidewalls of a silicon block left behind during the etching of the structure. The etching trenches are disposed at angles with respect to one another that are prescribed by the form of the silicon block left behind. Semiconductor layer structures which can interact with one another diagonally across are in each case accommodated in the etching trenches. In this case, the function of the entire circuit structure results from the interaction of the layer structures disposed in the various etching trenches.

公开(公告)号：DE10226583A1

公开(公告)日：2004-01-08

申请号：DE10226583

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: G11C7/00 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The large extent of the channel region in the bit line direction means that the trench capacitor can be rapidly charged and read. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. A conductive channel can be formed within the channel region depending on the potential of the word line.

公开(公告)号：DE10053425C2

公开(公告)日：2003-02-13

申请号：DE10053425

申请日：2000-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARX THILO ,  HEYNE PATRICK ,  PARTSCH TORSTEN ,  HEIN THOMAS ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  SOMMER MICHAEL

IPC: G11C8/08 ,  G11C8/10 ,  G11C8/18 ,  G11C8/00 ,  G11C7/00 ,  G11C11/407

公开(公告)号：DE10051937A1

公开(公告)日：2002-05-08

申请号：DE10051937

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  SOMMER MICHAEL ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  MARX THILO ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  HEIN THOMAS

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/133 ,  H03K5/14

Abstract: The circuit has input and output connections (1,2), first and second signal paths (3,4) with different delay times, a multiplexer (6), a drive circuit (5) with first and second programmable paths and transistors controled by complementary control signals and connected to nodes commonly connected to a multiplexer control input. Only one programmable path is programmed to be conducting and the other to be non-conducting.