公开(公告)号：DE102007001523A1

公开(公告)日：2008-07-17

申请号：DE102007001523

申请日：2007-01-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS ,  BAUMGARTL JOHANNES

IPC: H01L21/764

Abstract: The arrangement (1) has a semiconductor circuit (10) in or at a semiconductor material region (20) provided with two semiconductor circuit parts (11, 12). A void structure (30) is provided with a hollow cavity (31), which is arranged between semiconductor circuit parts. The hollow cavity is formed as a trench structure and is filled with inert gas. A semiconductor substrate (21) is arranged in the region. The semiconductor material region has a cover material region (24) that is provided with a wall or epitaxial layer (23). An independent claim is also included for a method for manufacturing a semiconductor circuit arrangement.

公开(公告)号：DE102006031538A1

公开(公告)日：2008-01-17

申请号：DE102006031538

申请日：2006-07-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS

IPC: H01L27/07

Abstract: The integrated semiconductor arrangement has a third semiconductor tub or semiconductor area of a conductivity type (p) is formed in a semiconductor tub (4a,4b) separated from the substrate, and is connected with an electrode structure of a power transistor, which is discrete metal oxide semiconductor, high voltage metal oxide semiconductor, vertical metal oxide semiconductor, down vertical metal oxide semiconductor, or a bipolar transistor. The power transistor is loaded with negative potential, so that the third semiconductor tub or the semiconductor area forms the collector. The reverse flow injecting electrode structure of the power transistor forms the base. The substrate forms the emitter of a parasitic bipolar transistor. The base of the bipolar transistor is short-circuited with collector and takes the electrode structure of the power transistor to the largest part of the reverse flow in the case of the negative potentials. An independent claim is also included for a method for producing integrated semiconductor arrangement.

公开(公告)号：DE10345247B4

公开(公告)日：2007-10-04

申请号：DE10345247

申请日：2003-09-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS ,  HOFMANN RENATE ,  BUSCH JOERG

IPC: H01L23/28 ,  H01L23/31 ,  H01L23/482 ,  H01L23/485 ,  H01L23/528

Abstract: Semiconductor component comprises a semiconductor body (2) having a semiconductor base surface (1), a pressing composition (3) for sealing the body and a claw structure for mechanically holding the pressing composition with the base surface. An independent claim is also included for a process for the production of a semiconductor component.

公开(公告)号：DE102005028951A1

公开(公告)日：2006-12-28

申请号：DE102005028951

申请日：2005-06-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LASKA THOMAS ,  STECHER MATTHIAS ,  BELLYNCK GREGORY ,  HOSSEINI KHALIL ,  MAHLER JOACHIM

IPC: H01L23/49 ,  H01L25/07 ,  H01R4/02 ,  H01R43/02

Abstract: The arrangement has a metallic layer (7) applied before producing an electrical connection between a semiconductor circuit arrangement (1) and an external contact device (3). The metallic layer is arranged on a surface of an internal contact terminal (4) and on a surface of a wire (6). A bottom of the semiconductor circuit arrangement and a top side of the external contact device are placed opposite to one another. The internal contact terminal is connected to an external contact terminal (5) of the external contact device by the wire. An independent claim is also included for a method for producing a connection arrangement.

公开(公告)号：DE10360513B4

公开(公告)日：2005-10-06

申请号：DE10360513

申请日：2003-12-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STECHER MATTHIAS

IPC: H01L23/36 ,  H01L23/367 ,  H01L23/522 ,  H01L27/085 ,  H01L29/417 ,  H01L29/78

Abstract: An integrated semiconductor circuit chip comprises at least one DMOS power transistor whose electrodes pass vertically to contact thick conductive metal rails (6,7) on the surface and comprise metallization planes giving thick high-current heat-conductive, HS-WL, layers (10-12) with large surface contact regions (A1-A3).

公开(公告)号：DE10106073A1

公开(公告)日：2002-08-29

申请号：DE10106073

申请日：2001-02-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  STECHER MATTHIAS

IPC: H01L27/12 ,  H01L29/06 ,  H01L29/73 ,  H01L29/78 ,  H01L29/786 ,  H01L29/861

Abstract: A semiconductor component has a semiconductor substrate, an insulation layer located on the semiconductor substrate, and a semiconductor layer that is arranged on the insulation layer. A first doped terminal zone, a second doped terminal zone, and a drift zone are formed in the semiconductor layer between the first and second terminal zones. At least one of the first and second terminal zones directly adjoins the semiconductor substrate.

公开(公告)号：DE10014659A1

公开(公告)日：2001-10-11

申请号：DE10014659

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： VIETZKE DIRK ,  STECHER MATTHIAS ,  SCHULZE HANS-JOACHIM ,  PERI HERMANN ,  NELLE PETER ,  PLOSS REINHARD ,  KANERT WERNER

IPC: H01L21/762 ,  H01L27/088 ,  H01L29/32 ,  H01L29/78 ,  H01L27/08 ,  H01L29/04 ,  H01L29/06

Abstract: The semiconducting circuit arrangement has a substrate (10) of a first conductor type (p) and a component region (20) on the front side of the substrate with a number of insulated troughs (25,26,28) of a second conductor type (n). At least one power component in the component region has a load connection (25) of the second conductor type for connecting a load. The substrate has a recombination zone (RZ) for the recombination of minority carriers injected into the substrate from the load connection.

公开(公告)号：DE19953883A1

公开(公告)日：2001-05-23

申请号：DE19953883

申请日：1999-11-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： NELLE PETER ,  STECHER MATTHIAS ,  HIRLER FRANZ ,  VIETZKE DIRK

IPC: H01L21/205 ,  H01L29/161 ,  H01L29/167 ,  H01L29/78

Abstract: The invention relates to a system for reducing the closing resistance of p-channel or n-channel field effect transistors by highly doping the semiconductor substrate (1). In order to prevent misfit caused by the high level of doping, the semiconductor substrate (1) is additionally doped with germanium or with carbon that serve to compensate for the misfit.