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    41.
    发明专利
    未知

    公开(公告)号：DE10128481A1

    公开(公告)日：2003-01-02

    申请号：DE10128481

    申请日：2001-06-12

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS ,  SELL BERNHARD ,  HECHT THOMAS

    IPC: B44C1/22 ,  C03C25/68 ,  G03F7/26 ,  H01L21/308 ,  H01L21/31

    Abstract: An etching mask is produced for etching a substrate by a photoresist layer being exposed such that areas which are exposed once are not yet completely exposed and, on the basis of a reflective layer which is located under the photoresist layer, additionally exposed areas are exposed completely. In consequence, a first etching mask which is used for etching a substrate can be renewed by a second etching mask in that a photoresist layer which is applied to the first etching mask or instead of the first etching mask is exposed such that areas which have been exposed once are not yet completely exposed, and areas which have been additionally exposed on the basis of a reflective layer which is located under the photoresist layer and corresponds to the first etching mask are exposed completely.

    42.
    发明专利
    未知

    公开(公告)号：DE10100582A1

    公开(公告)日：2002-07-18

    申请号：DE10100582

    申请日：2001-01-09

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS ,  LUETZEN JOERN

    IPC: H01L27/108 ,  H01L21/20 ,  H01L21/8242

    Abstract: A method for the production of trench capacitors, especially memory cells and at least one selection transistor for integrated semiconductor memories. According to the invention, the trench for the trench capacitor has a lower trench area in which the capacitor is arranged and an upper trench area in which an electrically conducting connection between an electrode of the capacitor to a diffusion area of the selection transistor is disposed.The inventive method reduces the number of process steps for the production of memory cells and enables the production of buried shrouds in the memory capacitors which exhibit the same insulation quality as that which is required for the production of highly integrated memory cells (diameter

    44.
    发明专利
    未知

    公开(公告)号：DE102005024855A1

    公开(公告)日：2006-12-07

    申请号：DE102005024855

    申请日：2005-05-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： JASCHIK STEFAN ,  AVELLAN ALEJANDRO ,  SCHROEDER UWE ,  ORTH ANDREAS ,  GOLDBACH MATTHIAS ,  STORBECK OLAF ,  STADTMUELLER MICHAEL ,  HECHT THOMAS

    IPC: H01L21/8242

    Abstract: Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

    46.
    发明专利
    未知

    公开(公告)号：DE10326805A1

    公开(公告)日：2005-01-13

    申请号：DE10326805

    申请日：2003-06-13

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

    IPC: H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788 ,  H01L27/115 ,  H01L21/8247

    Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

    Trench capacitor comprises a dielectric arranged between a first capacitor electrode and a second capacitor electrode
    48.
    发明专利
    Trench capacitor comprises a dielectric arranged between a first capacitor electrode and a second capacitor electrode 未知

    公开(公告)号：DE10147120A1

    公开(公告)日：2003-04-17

    申请号：DE10147120

    申请日：2001-09-25

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SELL BERNHARD ,  GOLDBACH MATTHIAS ,  LUETZEN JOERN ,  HECHT THOMAS

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Trench capacitor comprises a dielectric (23, 28) arranged between a first capacitor electrode (24) and a second capacitor electrode (16). The first capacitor electrode has a tubular structure which protrudes into a substrate (10). The second capacitor electrode has a first section (30, 32) which lies opposite the inner side of the tubular structure over the dielectric, and a second section which lies opposite the outer side of the tubular structure over the dielectric. An Independent claim is also included for a process for the production of the trench capacitor. Preferred Features: The substrate is of a first doping type. The second section of the second capacitor electrode has doped regions of a second doping type. The first section of the second capacitor electrode has a metal layer. The dielectric is made from a nitride-oxide layer sequence or an oxide-nitride-oxide layer sequence.

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