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    41.
    发明专利
    未知

    公开(公告)号：IT1319037B1

    公开(公告)日：2003-09-23

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  GREGORI STEFANO ,  PIERIN ANDREA ,  MICHELONI RINO ,  CORONINI SERGIO ,  TORELLI GUIDO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    42.
    发明专利
    未知

    公开(公告)号：DE69626804D1

    公开(公告)日：2003-04-24

    申请号：DE69626804

    申请日：1996-06-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CALLIGARO CRISTIANO ,  TELECCO NICOLA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  H03K5/13

    Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block (RC) connected to an input terminal (ATD) for memory address line transition signals. The delay block drives a counter (CONT) which feedback controls the control block through a combinational logic circuit (COMB_SCA) connected to the output terminal (OUT_RC) of the programmable delay block. A logic output circuit (COMB_OUT), connected to the output terminal of the delay block and to the counter, generates the timing signals (OUT).

    43.
    发明专利
    未知

    公开(公告)号：ITMI20002337A1

    公开(公告)日：2002-04-29

    申请号：ITMI20002337

    申请日：2000-10-27

    Applicant: ST MICROELECTRONICS SRL

    Inventor： TORELLI GUIDO ,  MICHELONI RINO ,  KHOURI OSAMA ,  PIERIN ANDREA ,  GREGORI STEFANO ,  CORONINI SERGIO

    IPC: G11C7/06 ,  G11C11/56 ,  G11C16/28 ,  G11C27/00

    Abstract: A circuit for reading a non-volatile memory cell has an output terminal for providing an output current, and a control terminal for receiving a voltage for controlling the output current. The reading circuit includes a feedback circuit which can be connected electrically to the output terminal and to the control terminal to generate the control voltage from a reference signal and from the output current. The feedback circuit also includes a current-amplification circuit having a first terminal for receiving a current-error signal derived from the reference signal and from the output current, and a second terminal for supplying an amplified current.

    45.
    发明专利
    未知

    公开(公告)号：ITTO990994A1

    公开(公告)日：2001-05-16

    申请号：ITTO990994

    申请日：1999-11-16

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  MICHELONI RINO ,  SACCO ANDREA ,  TORELLI GUIDO

    IPC: G11C5/14 ,  G11C11/56 ,  G11C16/30

    Abstract: The voltage generator comprises a negative feedback loop including a programmable voltage divider having a feedback node. The voltage divider comprises a programmable resistor disposed between the output of the voltage generator and the feedback node and having variable resistance. The programmable resistor includes a fixed resistor and a plurality of additional resistors arranged in series with each other and defining a plurality of intermediate nodes. The additional resistors may be selectively connected by means of switches disposed between the output of the voltage generator and a respective intermediate node so as to define an output voltage V0 programmable on the basis of command signals supplied to the switches.

    46.
    发明专利
    未知

    公开(公告)号：ITMI20002018D0

    公开(公告)日：2000-09-15

    申请号：ITMI20002018

    申请日：2000-09-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： KHOURI OSAMA ,  TORELLI GUIDO ,  MANSTRETTA ALESSANDRO

    IPC: G11C7/06 ,  G11C16/28

    Abstract: A reading circuit for semiconductor non-volatile memories connected to at least one selected cell and at least one reference cell, the circuit including current/voltage conversion circuits receiving a first current flowing through the selected cell and a second current flowing through the reference cell and providing respectively on a first circuit node a first selected cell voltage and on a second node a second reference cell voltage, at least one differential amplifier connected at the input of the first and the second nodes and having an output terminal to provide a logic signal correlated to the selected cell information, a first voltage-controlled discharge switch circuit connected to the first node and to a voltage reference, a second switch circuit connected to the second node and the voltage reference, and first and second voltage comparator circuits receiving the first selected cell voltage and the second reference cell voltage.

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