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    Fabrication of a Silicon-on-Insulator or Silicon-on-Nothing substrate for a semiconductor device involves forming a tunnel between a silicon layer and an initial substrate after defining and masking active zones and forming trenches
    51.
    发明专利
    Fabrication of a Silicon-on-Insulator or Silicon-on-Nothing substrate for a semiconductor device involves forming a tunnel between a silicon layer and an initial substrate after defining and masking active zones and forming trenches 未知

    公开(公告)号：FR2812764A1

    公开(公告)日：2002-02-08

    申请号：FR0010176

    申请日：2000-08-02

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  HAOND MICHEL ,  DUTARTRE DIDIER

    IPC: H01L21/762 ,  H01L21/328

    Abstract: Substrate production involves epitaxially growing semiconductor layers on an initial substrate (1), defining and masking active zones, forming spacers and trenches, lateral etching of the first epitaxial layer, filling the formed tunnel with a dielectric for a Silicon-On-Insulator (SOI) substrate or leaving void for a Silicon-On-Nothing (SON) substrate, and filling the trenches with a dielectric. Production of a SOI substrate involves: (a) epitaxial growth, in sequence, of a Ge or SiGe layer and a Si layer (3) on an initial, preferably Si, substrate; (b) defining and masking active zones; (c) forming insulating spacers (7) in trench zones around the perimeter of each active zone at predetermined intervals and back-to-back with the sides of the active zones; (d) etching the trenches; (e) lateral etching of the Ge or SiGe layer; (f) filling the formed laterally etched space (tunnel) (8) with a dielectric, preferably SiO2, or passivation of tunnel walls followed by filling the tunnel (8) with a dielectric different from SiO2; (g) filling the trenches with a dielectric, preferably SiO2; and (h) performing finishing operations. Production of a SON substrate involves the same procedure except that stage (f) is omitted and passivation of the tunnel walls can be carried out prior to filling the trenches with a dielectric. The thickness of the Ge or SiGe layer is 1-50 nm, preferably 10-30 nm, and the thickness of the Si layer (3) is 10-50 nm, preferably 5-20 nm. Following the finishing operations a 'bulk' zone is produced in the SOI or SON substrate by masking, using a resin, the region that must be retained, followed by removal of layers in the unmasked region. A multilayer of alternating Si layers (3) and Ge or SiGe layers (2) can be formed in stage (a) of the SOI or SON substrate production process. Independent claims are given for: (i) a substrate having at least one active SOI active zone surrounded by isolating trenches; and (ii) a substrate having at least one active SOI active zone surrounded by isolating trenches.

    Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region
    52.
    发明专利
    Fabrication of MOS transistor having two gates, one being buried, includes forming semiconductor channel region transversely mounting a first gate, and forming second gate on channel region 未知

    公开(公告)号：FR2806833A1

    公开(公告)日：2001-09-28

    申请号：FR0003844

    申请日：2000-03-27

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

    IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

    Abstract: MOS transistor production includes: forming first gate (2) in silicon-on-insulator substrate (1); forming semiconducting channel region transversely surmounting first gate, and drain (16) and source (17) regions respectively on each side of channel region; isolating channel region from upper surface of first gate; and forming the second gate (10) on, and transversely to, the channel region. Fabrication of a MOS transistor comprising a channel region sandwiched between a first gate (2) and a second gate (10) includes: (a) forming the first gate (2) in the body of a silicon-on-insulator (SOI) substrate (1); (b) on the upper surface of the substrate, forming by epitaxy a semiconducting channel region transversely surmounting the first gate (2), and semiconducting drain (16) and source (17) regions arranged respectively on each side of the channel region; (c) isolating the channel region from the upper surface of the first gate (2) by forming a tunnel under the channel region, and then filling it, at least partially, with a first dielectric material (8); and (d) forming the second gate (10) on the channel region and transversely to channel region, the second gate being separated from the upper surface of the channel region by a second dielectric material (8). An Independent claim is given for a MOS transistor produced by the above process. The thickness of dielectric material filling the tunnel produced in the MOS transistor is 1-50 nm, e.g. 20 nm.

    53.
    发明专利
    未知

    公开(公告)号：FR2802705A1

    公开(公告)日：2001-06-22

    申请号：FR9915902

    申请日：1999-12-16

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  DUTARTRE DIDIER

    IPC: H01L21/20 ,  H01L21/762 ,  H01L29/06 ,  H01L21/3213 ,  B82B1/00 ,  B82B3/00

    Abstract: The process for fabricating a network of nanometric lines made of single-crystal silicon on an isolating substrate includes the production of a substrate comprising a silicon body having a lateral isolation defining a central part in the body. A recess is formed in the central part having a bottom wall made of dielectric material, a first pair of opposed parallel sidewalls made of dielectric material, and a second pair of opposed parallel sidewalls. At least one of the opposed parallel sidewalls of the second pair being formed from single-crystal silicon. The method further includes the epitaxial growth in the recess, from the sidewall made of single-crystal silicon of the recess, of an alternating network of parallel lines made of single-crystal SiGe alloy and of single-crystal silicon. Also, the lines made of single-crystal SiGe alloy are etched to form in the recess a network of parallel lines made of single-crystal silicon insulated from each other.

    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE
    56.
    发明专利
    SYSTEME DE CONVERSION D'ENERGIE THERMIQUE EN ENERGIE ELECTRIQUE A EFFICACITE AMELIOREE 未知

    公开(公告)号：FR2982424B1

    公开(公告)日：2014-01-10

    申请号：FR1160209

    申请日：2011-11-09

    Applicant: COMMISSARIAT ENERGIE ATOMIQUE ,  ST MICROELECTRONICS SA

    Inventor： MONFRAY STEPHANE ,  SAVELLI GUILLAUME ,  SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  GAILLARD FREDERIC

    IPC: H01L37/00

    Abstract: Système de conversion d'énergie thermique en énergie électrique (S1) destiné à être disposé entre une source chaude (SC) et une source froide (SF) , comportant des moyens de conversion de l'énergie thermique en énergie mécanique (6) et un matériau piézoélectrique, les moyens de conversion de l'énergie thermique en énergie mécanique (6) comportant des groupes (G1, G2 ) de au moins trois bilames (9, 11, 13) reliés mécaniquement entre eux par leur extrémités longitudinales et suspendus au-dessus d'un substrat (12), chaque bilame (9, 11, 13) comportant deux états stables dans lesquels il présente dans chacun des états une courbure, deux bilames directement adjacentes (9, 11, 13) présentant pour une température donnée des courbures opposées, le passage d'un état à stable des bilames (9, 11, 13) à l'autre provoquant la déformation d'un matériau piézoélectrique.

    57.
    发明专利
    未知

    公开(公告)号：FR2838866B1

    公开(公告)日：2005-06-24

    申请号：FR0205073

    申请日：2002-04-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CORONEL PHILIPPE ,  LEVERD FRANCOIS ,  SKOTNICKI THOMAS

    IPC: H01L21/02 ,  H01L21/3213 ,  H01L21/336 ,  H01L21/68 ,  H01L21/762 ,  H01L21/8242 ,  H01L23/544 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L51/00 ,  H01L51/40 ,  H01L21/70 ,  H01L27/108

    Abstract: Fabrication of an integrated electronic component comprises: producing an initial structure (SI) incorporating volumes of respective materials forming a definite pattern (M) on a first substrate; transferring the pattern to a second substrate (200); and producing, on the second substrate surface, an additional structure by using the volumes of the materials of the pattern as alignment markers. Fabrication of an integrated electronic component comprises: (a) producing, on the surface of a first substrate (100), an initial structure (SI) incorporating volumes of respective materials, at least part of the volumes forming a definite pattern (M); (b) transferring at least a part of the initial structure (SI) comprising the pattern of the first substrate (100) to a second substrate (200); and (c) producing, on the surface of the second substrate (200), an additional structure by using at least some of the volumes of the materials of the pattern (M) as alignment markers. Independent claims are given for: (i) an integrated electronic component obtained by the invented process; and (ii) an electronic device comprising a transistor, or a diode, or a dynamic random access memory (DRAM) element.

    58.
    发明专利
    未知

    公开(公告)号：FR2838238B1

    公开(公告)日：2005-04-15

    申请号：FR0204358

    申请日：2002-04-08

    Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

    Inventor： CORONEL PHILIPPE ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS

    IPC: H01L21/336 ,  H01L29/786

    Abstract: The device comprises a semiconductor substrate (SB), a base insulator layer (BOX) formed on the substrate, a semiconductor channel region extending in longitudinal direction and enveloping the channel region. The regions of source (S), channel (CN) and drain (D) are formed in a continuous semiconductor layer (200) which is substantially flat and parallel to the upper surface of the substrate (SB), and the region of source, drain and gate (80) are encapsulated so to ensure an electrical insulation between the gate region and the regions of source and drain, and also between the substrate and the regions of source, drain, gate and channel. The thickness of the continuous semiconductor layer (200) is of the order of tens of nanometers. The gate region (80) is continuous, or formed of upper layer and lower parts separated by a dielectric layer. Independent claims are also included for: (1) an integrated circuit comprising the semiconductor device; and (2) a method for manufacturing the device comprising the formation of the base insulator layer, the formation of a silicon layer encapsulated between two layers, anisotropic etching, selective isotropic etching, filling tunnels with dielectric material, anisotropic etching, total selective etching of the remainders of encapsulation layers, oxidation of remainder of silicon layer, and filling spaces resulting from etching with the gate material.

    60.
    发明专利
    未知

    公开(公告)号：FR2800913B1

    公开(公告)日：2004-09-03

    申请号：FR9914105

    申请日：1999-11-10

    Applicant: ST MICROELECTRONICS SA

    Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  MALLARDEAU CATHERINE

    IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/92 ,  H01G4/33 ,  H01G4/38

    Abstract: The invention concerns a method which consists in forming on a substrate ( 1 ) coated with a dielectric material layer ( 3 ) provided with a window ( 3 a), a stack of successive layers alternately of germanium or SiGe alloy ( 4, 6, 8 ) and polycrystalline silicon ( 5, 7, 9 ); selective partial elimination of the germanium or SiGe alloy layers, to form an tree-like structure; forming a thin layer of dielectric material ( 10 ) on the tree-like structure; and coating the tree-like structure with polycrystalline silicon ( 11 ). The invention is useful for making dynamic random-access memories.

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