公开(公告)号：KR1020120073836A

公开(公告)日：2012-07-05

申请号：KR1020100135721

申请日：2010-12-27

Applicant: 주식회사 실리콘웍스

Inventor： 김지훈 ,  손영준 ,  나준호 ,  장영신 ,  이상국

IPC: H03M1/38

CPC classification number: H03M1/38 ,  H03M1/14 ,  H03M1/187 ,  H03M2201/2233 ,  H03M2201/62 ,  H03M2201/93

Abstract: PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) is provided to reduce an installation space by using voltage division resistance instead of using a capacitor array. CONSTITUTION: A preamp part(210) includes first and second MOS transistors(M1,M2) differentially amplify a positive input voltage and a negative input voltage, respectively. A digital/analog converter(240) includes third and fourth MOS transistors(M3,M4) which differentially amplify the output voltage of a voltage divider(241). A SAR control unit(230) outputs a distribution voltage selection signal for selecting a positive DA voltage and a negative DA voltage according to output bit values of a quantizer(220). The quantizer outputs bit values by comparing output currents. The D/A converter selects the positive DA voltage and the negative DA voltage according to the distribution voltage selection signal. The D/A converter changes the output current by differentially amplifying the selected voltage.

Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模数转换器），通过使用分压电阻而不是使用电容阵列来减少安装空间。 构成：前置放大器部分（210）包括第一和第二MOS晶体管（M1，M2）分别差分放大正输入电压和负输入电压。 数字/模拟转换器（240）包括差分放大分压器（241）的输出电压的第三和第四MOS晶体管（M3，M4）。 SAR控制单元（230）根据量化器（220）的输出位值输出用于选择正的DA电压和负的DA电压的分配电压选择信号。 量化器通过比较输出电流输出位值。 D / A转换器根据分配电压选择信号选择正的DA电压和负的DA电压。 D / A转换器通过差分放大所选择的电压来改变输出电流。

公开(公告)号：KR1020120021772A

公开(公告)日：2012-03-09

申请号：KR1020100079077

申请日：2010-08-17

Applicant: 서강대학교산학협력단

Inventor： 이승훈

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M1/002 ,  H03M2201/62 ,  H03M2201/6372 ,  H03M2201/644

Abstract: PURPOSE: A DAC(Digital To Analog Converter) using a two-dimensional INL(Integral Non-Linearity) bounded switching method is provided to secure linearity at an INL property by minimizing glitch energy. CONSTITUTION: A DAC(Digital To Analog Converter) uses a two-dimensional INL(Integral Non-Linearity) bounded switching method based on a current cell matrix structure. The DAC changes an input digital signal to an analog output signal. The DAC switches current cells, which form each matrix, through a column and row decoding mode. Switching through the decoding method divides a cell matrix to be equal into two from side to side as well as an up and down. The switching through the decoding method preferentially switches the cells which are located in a first quadrant and a third quadrant of the cell matrix. The cells, which are located in a second quadrant and a fourth quadrant, are secondly switched.

Abstract translation: 目的：提供使用二维INL（积分非线性）有界切换方法的DAC（数模转换器），通过最小化毛刺能量来确保INL属性的线性度。 构成：DAC（数模转换器）使用基于当前单元矩阵结构的二维INL（积分非线性）有界切换方法。 DAC将输入数字信号改变为模拟输出信号。 DAC通过列和行解码模式切换形成每个矩阵的当前单元格。 通过解码方法切换将单元矩阵从一侧到另一侧以及上下划分成两个。 通过解码方法的切换优先地切换位于单元矩阵的第一象限和第三象限中的单元。 位于第二象限和第四象限中的单元被二次切换。

公开(公告)号：KR101116355B1

公开(公告)日：2012-03-09

申请号：KR20100113191

申请日：2010-11-15

Applicant: IUCF HYU ,  HYNIX SEMICONDUCTOR INC

Inventor： JEONG CHUN SEOK ,  KIM KYUNG WHAN ,  YOO CHANG SIK ,  LEE JANG WOO

IPC: H03M1/12

CPC classification number: H03M1/38 ,  H03M1/1009 ,  H03M2201/225 ,  H03M2201/62

Abstract: PURPOSE: A successive approximation register circuit and a successive approximation analog digital convertor including the same are provided to improve performance by reducing time which is taken to convert an analog signal into a digital signal. CONSTITUTION: A selecting unit(610) selects for a setting value of a first half period having the several times of scan periods. The selecting unit selects a reference value which is inputted at the scan period in a latter half period one by one. A register unit(620) includes a plurality of registers. A controlling unit(630) successively activates a register of the register unit at each scan period. The register activated among a plurality of registers(621,622,626) stores an output value of the selecting unit.

Abstract translation: 目的：提供逐次逼近寄存器电路和包括其的逐次逼近模拟数字转换器，以通过减少将模拟信号转换为数字信号所需的时间来提高性能。 构成：选择单元（610）选择具有多次扫描周期的前半个周期的设定值。 选择单元逐个选择在后半个时段的扫描周期输入的基准值。 寄存器单元（620）包括多个寄存器。 控制单元（630）在每个扫描周期连续激活寄存器单元的寄存器。 在多个寄存器（621,622,626）中激活的寄存器存储选择单元的输出值。

公开(公告)号：KR1020120013121A

公开(公告)日：2012-02-14

申请号：KR1020100075309

申请日：2010-08-04

Applicant: 서강대학교산학협력단

Inventor： 이승훈

IPC: H03M1/12

CPC classification number: H03M1/122 ,  H03M1/002 ,  H03M2201/2216 ,  H03M2201/62

Abstract: PURPOSE: An ADC(Analog-to-Digital Converter) having common capacitors and a common amplifier is provided to secure a stabilized operation by properly regulating the transconductance of the common amplifier. CONSTITUTION: An SHA(Sample-and-Hold Amplifier) and an MDAC(Multiplying D/A Converter) constituting the input terminal of an ADC uses two capacitor rows and one amplifier in common. Unnecessary one of the two capacitor rows is reset according to the operating mode of the ADC. The amplifier has two input terminals, unnecessary one of which is reset according to the operating mode of the ADC.

Abstract translation: 目的：提供具有公共电容器和公共放大器的ADC（模数转换器），以通过适当地调节公共放大器的跨导来确保稳定的操作。 构成：组成ADC的输入端的SHA（采样保持放大器）和MDAC（乘法D / A转换器）使用两个电容器行和一个放大器。 根据ADC的工作模式，两个电容行中的不必要的一个复位。 放大器有两个输入端子，根据ADC的工作模式，不必要的一个输入端子被复位。

公开(公告)号：KR1020080107829A

公开(公告)日：2008-12-11

申请号：KR1020070056120

申请日：2007-06-08

Applicant: 재단법인서울대학교산학협력재단 ,  주식회사 시너칩

Inventor： 김수환 ,  정덕균 ,  우종관 ,  신동용 ,  최원준

IPC: H03M1/66

CPC classification number: H03M1/662 ,  H03M2201/16 ,  H03M2201/311 ,  H03M2201/3157 ,  H03M2201/62

Abstract: A segmented digital to analog converter is provided to perform the miniaturization by reducing the number of the switches used in a coarse digital to analog converter. A segmented DAC(Digital to Analog Converter)(100) includes a first digital to analog converter, and a second digital-to-analog converter. The first digital to analog converter includes a first output terminal and a second output terminal. The first output terminal outputs a first coarse voltage. The second output terminal outputs a second coarse voltage. The second digital to analog converter outputs a minute voltage obtained by interpolating the first coarse voltage and the second coarse voltage. The first digital to analog converter includes a register string(110), and a first switch unit(120). The register string includes a plurality of resisters which are serially connected. The register string outputs a plurality of reference voltages. The first switch unit outputs two consecutive reference voltages selected among the plurality of the reference voltages as the first and second coarse voltages. The first coarse voltage is selected among odd-number reference voltages among the plurality of reference voltages. The second coarse voltage is selected among even-number reference voltages among the plurality of reference voltages.

Abstract translation: 提供分段数模转换器以通过减少粗略数模转换器中使用的开关数量来执行小型化。 分段DAC（数模转换器）（100）包括第一数模转换器和第二数/模转换器。 第一数模转换器包括第一输出端和第二输出端。 第一输出端输出第一粗电压。 第二输出端输出第二粗电压。 第二数模转换器输出通过内插第一粗电压和第二粗电压而获得的微小电压。 第一数模转换器包括寄存器串（110）和第一开关单元（120）。 寄存器串包括串联连接的多个电阻。 寄存器串输出多个参考电压。 第一开关单元输出在多个参考电压中选择的两个连续的参考电压作为第一和第二粗略电压。 第一粗略电压在多个参考电压中的奇数参考电压中选择。 第二粗电压在多个参考电压中的偶数参考电压中选择。

公开(公告)号：KR1020080105977A

公开(公告)日：2008-12-04

申请号：KR1020080016598

申请日：2008-02-25

Applicant: 삼성전자주식회사

Inventor： 고주현 ,  정지운 ,  김종선

IPC: H03M1/66

CPC classification number: H03M1/664 ,  H03M2201/31 ,  H03M2201/62 ,  H03M2201/932 ,  H04N5/202

Abstract: A digital-analog converter and a digital-analog converting method are provided to obtain a nonlinear output characteristic approximated to a gamma curve of an LCD panel. An integrated circuit includes an operational amplifier(251), a first capacitor(Csa), a plurality of second capacitors(270), and a switching circuit(280). The operational amplifier includes a first input terminal, a second input terminal and an output terminal. The first capacitor includes a first terminal and a second terminal. The second terminal is connected to a first input terminal of the operational amplifier. The second capacitor includes the first terminal and the second terminal. The second terminal is connected to the second input terminal of the operational amplifier. The switching circuit includes the plurality of switches which are switched by responding to a corresponding switching signal among the plurality of switching signals. The switching circuit transmits the reference voltage to the first terminal of the first capacitor and the respective first terminals of the second capacitors. The switching circuit connects the first input terminal of the operational amplifier to the output terminal of the operational amplifier. The switching circuit separates the reference voltage from the first terminal of the first capacitor for the second section and transmits the selected voltage of two selection voltage or more to the respective first terminal of the second capacitors. The first terminal of the first capacitor is connected to the output terminal of the operational amplifier.

Abstract translation: 提供数字 - 模拟转换器和数字 - 模拟转换方法以获得近似于LCD面板的伽马曲线的非线性输出特性。 集成电路包括运算放大器（251），第一电容器（Csa），多个第二电容器（270）和开关电路（280）。 运算放大器包括第一输入端，第二输入端和输出端。 第一电容器包括第一端子和第二端子。 第二端子连接到运算放大器的第一输入端。 第二电容器包括第一端子和第二端子。 第二端子连接到运算放大器的第二输入端。 开关电路包括通过响应多个开关信号中的相应开关信号来切换的多个开关。 开关电路将参考电压发送到第一电容器的第一端子和第二电容器的相应的第一端子。 开关电路将运算放大器的第一输入端连接到运算放大器的输出端。 开关电路将参考电压与第二部分的第一电容器的第一端分开，并将所选择的两个选择电压以上的电压发送到第二电容器的相应的第一端。 第一电容器的第一端连接到运算放大器的输出端。

公开(公告)号：KR1020080004807A

公开(公告)日：2008-01-10

申请号：KR1020060063579

申请日：2006-07-06

Applicant: 한국과학기술원

Inventor： 조규형 ,  전용준 ,  손영석 ,  전진용 ,  이건호

IPC: H03M1/66

CPC classification number: H03M1/66 ,  H03M2201/61 ,  H03M2201/62 ,  H03M2201/81

Abstract: A current supply circuit and a digital analog converter provided with the same are provided to prevent the distortion of an output current caused by changes or ununiformity in a semiconductor process. A current supply circuit includes a corrector(310) and a current source unit(320). The corrector(310) includes a reference current source(ISRC1) and a reference current generator(3010). The reference current generator receives the reference current source to generate reference current. The current source part includes a first switch(SW1), a correction current generator(3020), a second switch(SW2), and a buffer(3000). The first switch is electrically connected with one of the reference current source and an output terminal. The correction current generator generates corrected current in accordance with the reference current generator. The second switch electrically connects the reference current generator and the correction current generator. The buffer is electrically connected between the first switch and the correction current generator.

Abstract translation: 提供电流供给电路和设置有电流供给电路的数字模拟转换器，以防止由半导体工艺中的变化或不均匀性引起的输出电流的失真。 电流源电路包括校正器（310）和电流源单元（320）。 校正器（310）包括参考电流源（ISRC1）和参考电流发生器（3010）。 参考电流发生器接收参考电流源以产生参考电流。 电流源部分包括第一开关（SW1），校正电流发生器（3020），第二开关（SW2）和缓冲器（3000）。 第一开关与参考电流源和输出端之一电连接。 校正电流发生器根据参考电流发生器产生校正电流。 第二开关电连接参考电流发生器和校正电流发生器。 缓冲器电连接在第一开关和校正电流发生器之间。

公开(公告)号：KR1020070082354A

公开(公告)日：2007-08-21

申请号：KR1020060015081

申请日：2006-02-16

Applicant: 삼성전자주식회사

Inventor： 송태익 ,  신용원 ,  임종한 ,  이종훈

IPC: H03M1/66 ,  H04B1/40

CPC classification number: H03M1/70 ,  H03M2201/196 ,  H03M2201/6107 ,  H03M2201/62

Abstract: An apparatus and a method for controlling a dynamic range of a DAC(Digital to Analog Converter) input signal are provided to optimize the performance of a DAC by actively controlling the DAC input signal according to the number of channels and operation scenarios. Diffused signals including a plurality of channel signals having predetermined digital gain values outputted by a PN diffuser(202) pass through a gain normalizer(204) before transmission to an LPF(Low Pass Filter)(206). The gain normalizer(204) normalizes the diffused signals of N + m bits with normalization factors in accordance with an input operation range of a DAC(210) to output normalized signals of N bits. The PN diffuser(202) generates the diffused signals of larger bits that is N+m bits by using the gain normalizer(204). The output of the gain normalizer(204) is filtered by the LPF(206) to be transmitted to an interpolator(208). The interpolator(208) interpolates the signals transmitted from the LPF(206) in consideration of the input operation range of the DAC(210) to provide the interpolated signals to the DAC(210). The DAC(210) converts the interpolated signals into analog signals and outputs the converted signals.

Abstract translation: 提供了一种用于控制DAC（数模转换器）输入信号的动态范围的装置和方法，以通过根据信道数量和操作情况主动地控制DAC输入信号来优化DAC的性能。 包括具有由PN扩散器（202）输出的预定数字增益值的多个信道信号的扩散信号在传输到LPF（低通滤波器）（206）之前经过增益归一化器（204）。 增益归一化器（204）根据DAC（210）的输入操作范围使归一化因子对N + m位的扩散信号进行归一化，以输出N位的归一化信号。 PN漫射器（202）通过使用增益归一化器（204）产生N + m比特的较大比特的扩散信号。 增益归一化器（204）的输出由LPF（206）滤波以被发送到内插器（208）。 考虑到DAC（210）的输入操作范围，插值器（208）内插从LPF（206）发送的信号，以将内插信号提供给DAC（210）。 DAC（210）将内插信号转换为模拟信号并输出​​转换后的信号。

公开(公告)号：KR1020070058395A

公开(公告)日：2007-06-08

申请号：KR1020070041228

申请日：2007-04-27

Applicant: 주식회사 애트랩

Inventor： 이방원 ,  신영호

IPC: H03M1/50 ,  H03M1/12

CPC classification number: H03M1/50 ,  H03M1/34 ,  H03M2201/32 ,  H03M2201/62

Abstract: An analog-digital converter is provided to reduce a size and power consumption by using a small number of analog elements in comparison with a conventional analog-digital converter. An analog-digital converter includes a measurement signal generator(71), a variable delay unit(72), a fixed delay unit(73), and a delay calculating and data generating unit(80). The measurement signal generator(71) generates a measurement signal(in). When the generated measurement signal(in) is changed from a low level to a high level, a switch(SW) of the variable delay unit(72) connects a ground voltage and a first capacitor(C1). The variable delay unit(72) generates a sensing signal(sen) by delaying the measurement signal(in) for a first delay. The fixed delay unit(73) generates a reference signal(ref) by delaying the measurement signal(in) for a second delay. The delay calculating and data generating unit(80) calculates a delay difference between the reference signal(ref) and the sensing signal(sen), and generates digital data having a value corresponding to the calculated delay difference.

Abstract translation: 提供了一种模拟数字转换器，用于通过使用少量的模拟元件与传统的模数转换器相比来减小尺寸和功耗。 模拟数字转换器包括测量信号发生器（71），可变延迟单元（72），固定延迟单元（73）和延迟计算和数据生成单元（80）。 测量信号发生器（71）产生测量信号（in）。 当所生成的测量信号（in）从低电平变为高电平时，可变延迟单元（72）的开关（SW）连接接地电压和第一电容器（C1）。 可变延迟单元（72）通过将测量信号（in）延迟第一延迟来产生感测信号（sen）。 固定延迟单元（73）通过将测量信号（in）延迟第二延迟来产生参考信号（ref）。 延迟计算和数据生成单元（80）计算参考信号（ref）和感测信号（sen）之间的延迟差，并产生具有与计算出的延迟差对应的值的数字数据。

公开(公告)号：KR1020060099307A

公开(公告)日：2006-09-19

申请号：KR1020050020679

申请日：2005-03-11

Applicant: 엘지전자 주식회사

Inventor： 이우열

IPC: H03M1/68

CPC classification number: H03M1/662 ,  H03M1/002 ,  H03M1/361 ,  H03M2201/2216 ,  H03M2201/615 ,  H03M2201/62 ,  H03M2201/625 ,  H03M2201/814 ,  H03M2201/8152

Abstract: 주파수 특성을 보상하기 위한 보상용 콘덴서의 용량을 줄여 보상용 콘덴서의 면적을 줄이고, 12비트 이상의 고해상도를 가지는 신호를 왜곡됨이 없이 처리하는 MDAC(Multiplying Digital to analog converter)를 제공한다.
SHA(Sampling and Holding Amplifier) 또는 MDAC로부터 입력되는 신호에서 플래쉬 ADC(Analog to digital converter)가 디지털 신호로 변환한 레벨을 감산하는 감산기와, 제 1 바이어스 전압에 따라 정전류가 흐르는 제 1 및 제 2 정전류원과, 상기 제 1 정전류원으로 정전류가 흐르면서 상기 감산기의 출력신호를 캐스코드 증폭하는 제 1 증폭기와, 상기 제 1 증폭기의 증폭이득을 부스팅하여 증가시키는 제 1 및 제 2 부스팅용 증폭기와, 상기 제 2 정전류원으로 정전류가 흐르면서 상기 제 1 증폭기의 증폭신호를 차동 증폭하여 출력단자로 출력하는 제 2 증폭기와, 상기 제 1 및 제 2 증폭기의 사이에 구비되는 제 1 및 제 2 보상용 콘덴서로 이루어지는 것으로 제 1 및 제 2 보상용 콘덴서가 차지하는 면적 및 소모전력을 줄이고, 고해상도의 신호를 왜곡이 발생됨이 없이 처리한다.
MDAC, ADC, 파이프라인 ADC, 보상용 콘덴서, DCL, 감산기, 부스팅용 증폭기