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    63.
    发明专利
    未知

    公开(公告)号：DE60139670D1

    公开(公告)日：2009-10-08

    申请号：DE60139670

    申请日：2001-04-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GREGORI STEFANO ,  MICHELONI RINO ,  PIERIN ANDREA ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C16/02 ,  G11C16/12 ,  G11C11/56

    Abstract: The method involves applying in succession, to a control terminal of the memory cell, at least two programming pulse trains (F1,F2) with pulse amplitude increasing in staircase fashion. The amplitude increment between one pulse and the next in the first programming pulse train (F1) is greater than the amplitude increment between one pulse and the next in the second programming pulse train (F2). Transition from the first programming pulse to train to the second is made when the memory cell has a threshold voltage with a pre-set relation with a reference value.

    66.
    发明专利
    未知

    公开(公告)号：DE69823982D1

    公开(公告)日：2004-06-24

    申请号：DE69823982

    申请日：1998-05-29

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MANSTRETTA ALESSANDRO ,  PIERIN ANDREA ,  TORELLI GUIDO

    IPC: G11C16/06 ,  G11C16/04 ,  G11C16/12

    Abstract: A selector switch monolithically integrated to a CMOS technology circuit for electrically programmable memory cell devices having at least first and second input terminals for coupling to first and second voltage generators (HV and LV), respectively, and an output terminal (OUT). First (P1) and second (P2) field-effect selection transistors are respectively connected, via first and second terminals, between the first input terminal and the output terminal and between the second input terminal and the output terminal. These transistors are driven through control terminals at non-overlapping phases and have body terminals connected at a body circuit node (BODY) which is coupled to the first and second voltage generators through a bias circuit block (WBC) effective to bias the node to the higher of the instant voltages generated by the first and second generators.

    67.
    发明专利
    未知

    公开(公告)号：IT1320699B1

    公开(公告)日：2003-12-10

    申请号：ITTO20000936

    申请日：2000-10-06

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MICHELONI RINO ,  GREGORI STEFANO ,  KHOURI OSAMA ,  TORELLI GUIDO

    IPC: G11C11/56 ,  G11C16/26 ,  G11C16/30

    Abstract: A multilevel nonvolatile memory includes a supply line (28) supplying a supply voltage (VDD), a voltage boosting circuit (26) supplying a boosted voltage (Vp), higher than the supply voltage (VDD), a boosted line (30) connected to the voltage boosting circuit (26) and a reading circuit (25) including at least one comparator (35). The comparator (35) includes a first and a second input (35a, 35b), a first and a second output (45a, 45b), at least one amplification stage (40) connected to the boosted line (30), and a boosted line latch stage (41) connected to the supply line (28).

    69.
    发明专利
    未知

    公开(公告)号：DE69232170T2

    公开(公告)日：2002-06-06

    申请号：DE69232170

    申请日：1992-06-26

    Applicant: ST MICROELECTRONICS SRL

    Inventor： MALOBERTI FRANCO ,  MARCHESI GIANMARCO ,  TORELLI GUIDO

    IPC: G11C11/417 ,  G11C7/10 ,  H03K17/04 ,  H03K17/16 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K19/00 ,  G11C7/00

    Abstract: The switching noise generated by a data output buffer is greatly reduced by "precharging" the output node to an intermediate voltage between a pre-existent logic level and a different logic level, during a system's "dead" time, with a precharging output current pulse having a constant time derivative during a first time interval and a constant time derivative of opposite sign during a second time interval, before performing the actual switching with an output current having a constant time derivative, during a third time interval. The partial charging or discharging of the load capacitance before actually performing a switching, with a controlled, triangular-shaped, output current pulse, avoids any abrupt change of output current and thus limits switching noise. The buffer of the invention is particularly useful in high-speed memory devices.

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