公开(公告)号：EP1233927A4

公开(公告)日：2003-01-08

申请号：EP00980528

申请日：2000-11-17

Applicant: UNIV CALIFORNIA

Inventor： HANSFORD DEREK ,  FERRARI MAURO

IPC: B82B3/00 ,  B01D67/00 ,  B01D69/02 ,  B01D71/02 ,  B81B3/00 ,  B81C1/00 ,  B01D63/00 ,  B01J29/06 ,  B82B1/00 ,  C01B37/00

CPC classification number: B81C1/00158 ,  B01D67/0058 ,  B01D67/0062 ,  B01D67/0072 ,  B01D69/02 ,  B01D71/02 ,  B01D71/022 ,  B01D2325/02 ,  B01D2325/04 ,  B01D2325/08 ,  B81B2201/06 ,  B81B2201/10 ,  B81C2201/0109 ,  B81C2201/014 ,  B81C2201/053

Abstract: A method of forming a membrane with nanometer scale pores includes forming a sacrificial etch stop layer on a substrate. A base layer is constructed on the sacrificial etch stop layer. Micrometer scale pores are formed within the base layer. A sacrificial base layer is built on the base layer. The sacrificial base layer is removed from selected regions of the base layer to define nanometer scale pores within the base layer. The resultant membrane has sub-fifty nanometer pores formed within it.

公开(公告)号：EP1257496A2

公开(公告)日：2002-11-20

申请号：EP00990587.8

申请日：2000-12-28

Applicant: ROBERT BOSCH GMBH

Inventor： FISCHER, Frank ,  HEIN, Peter ,  GRAF, Eckhard

IPC: B81B3/00 ,  G01P15/08 ,  B81C1/00

CPC classification number: B81C1/00801 ,  B81B2203/0136 ,  B81B2203/0315 ,  B81C2201/0109 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

Abstract: The invention relates to a method for producing a micromechanical component (100) that comprises at least one cavity (110) and one functional element (12) at least partially disposed in said cavity (110) and/or one functional layer (13a, 13b, 13c) at least partially disposed therein. The invention further relates to a micromechanical component (100) produced according to the inventive method. The aim of the invention is to reduce the production costs for such a micromechanical component. To this end, the functional element (12) and/or the functional layer (13a, 13b, 13c) is provided with a first protective layer (41; 71) at least in a zone that adjoins a first sacrificial coating (52) that temporarily occupies the space of the cavity (22) subsequently formed in one or more etching steps. The material of the first protective layer (41) is selected in such a manner that at least one etching method and/or etching agent etching or dissolving the first sacrificial coating (52) does substantially not corrode the first protective layer (41; 71) or corrodes it only at a reduced etching rate in relation to the first sacrificial coating (52).

公开(公告)号：EP0567075B1

公开(公告)日：2001-10-24

申请号：EP93106391.1

申请日：1993-04-20

Applicant: DENSO CORPORATION

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi ,  Tanizawa, Yukihiko

IPC: H01L21/306 ,  H01L21/78 ,  C25F3/12

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

公开(公告)号：EP0922944A3

公开(公告)日：1999-11-10

申请号：EP98830266.7

申请日：1998-04-30

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

IPC: G01L9/00

CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

公开(公告)号：EP0567075A3

公开(公告)日：1997-09-24

申请号：EP93106391.1

申请日：1993-04-20

Applicant: NIPPONDENSO CO., LTD.

Inventor： Fukada, Tsuyoshi ,  Yoshino, Yoshimi ,  Tanizawa, Yukihiko

IPC: H01L21/306 ,  H01L21/78 ,  H01L21/308

CPC classification number: B81C1/00888 ,  B81B2201/0235 ,  B81C1/00158 ,  B81C2201/0114 ,  B81C2201/053 ,  G01L9/0055 ,  G01P15/0802 ,  G01P15/123 ,  H01L21/3063 ,  H01L21/78 ,  Y10S148/028 ,  Y10S148/159 ,  Y10S438/977

Abstract: A method for producing a semiconductor device is capable of solving problems related to dicing a metal thin film used for electrochemical etching. According to the method, an n type epitaxial thin layer (36) is formed on a p type single-crystal silicon wafer (35). An n + type diffusion layer (38) is formed in a scribe line area on the epitaxial layer (36). An n + type diffusion layer (39) is formed in an area of the epitaxial layer (36) which corresponds to the predetermined part of the wafter (35). Aluminum film (40, 41) is formed over the diffusion layers (38, 39), respectively. The aluminum film (40) has a clearance (65) for passing a dicing blade (66). Predetermined parts of the wafer (35) are electrochemically etched by supplying electricity through the aluminum film (40), the diffusion layers (38) and (39), to leave predetermined parts of the epitaxial layer (36). The wafer (35) is diced into chips along the scribe line area. Each of the chips forms the semiconductor device. The electrochemical etching of the wafer (35) is carried out after the formation of the aluminum film (40, 41), by immersing the wafer (35) in a KOH aqueous solution (76) and by supplying electricity through the aluminum film (40). The electrochemical etching is terminated at an inflection point where an etching current inflects to a constant level from a peak level. During the electrochemical etching, the diffusion layer (39) reduces horizontal resistance in the epitaxial layer (36), so that the etched parts receive a sufficient potential to perform the etching.

Abstract translation: 公开了一种用于制造半导体器件的方法和装置，该半导体器件具有薄膜形式的隔膜和在同一衬底上具有电极的集成电路部分，所述方法包括：形成第二导电半导体层的第一步骤 在第一导电类型的单晶半导体衬底上; 在半导体层上形成具有电极的集成电路部分的第二步骤; 在半导体层上的划线区域中形成电极并将划线区域中的电极与集成电路部分的电极电连接的第三步骤; 通过在划线区域中的电极传输用于电化学蚀刻的电力来电化学蚀刻基板的预定部分，从半导体层形成隔膜的第四步骤，以及沿着划线区域将基板切割成芯片的第五步骤 ，形成半导体器件的每个芯片。

公开(公告)号：EP0683921A4

公开(公告)日：1997-01-02

申请号：EP94903348

申请日：1993-12-03

Applicant: CORNELL RES FOUNDATION INC

Inventor： SHAW KEVIN A ,  ZHANG Z LISA ,  MACDONALD NOEL C

IPC: C23F4/00 ,  B81B3/00 ,  G01P15/08 ,  G01P15/125 ,  H01L21/302 ,  H01L21/3065 ,  H01L29/82 ,  H01L29/84 ,  H01L21/44 ,  H01L21/449 ,  H01L23/48 ,  H01L29/06 ,  H01L29/86 ,  H01L29/96

CPC classification number: B81C1/00619 ,  B81C1/00142 ,  B81C1/0015 ,  B81C1/00626 ,  B81C2201/0112 ,  B81C2201/0132 ,  B81C2201/053 ,  G01P15/0802 ,  G01P15/125 ,  G01P2015/0814 ,  G01P2015/0817 ,  G01P2015/0828 ,  Y10S73/01 ,  Y10S148/05

Abstract: The invention provides a single mask, low temperature reactive ion etching process for fabricating high aspect ratio, released single crystal microelectromechanical structures independent of crystal orientation. A dielectric mask (12) on a single-crystal substrate (154) is patterned to define isolating trenches. A protective conformal layer (28) is applied to the resultant structure. The conformal layer (28) on the floor of the trenches is removed and a second etch deepens the trench to expose the mesa walls which are removed during the release step by isotropic etching. A metal layer (44) is formed on the resultant structure providing opposed plates (156) and (158) of a capacitor. The cantilever beam (52) with the supporting end wall (152) extends the grid-like structure (150) into the protection of the deepened isolation trenches (54). A membrane can be added to the released structures to increase their weight for use in accelerometers, and polished for use as movable mirrors.

公开(公告)号：WO2014202283A3

公开(公告)日：2015-02-26

申请号：PCT/EP2014059633

申请日：2014-05-12

Applicant: EPCOS AG

Inventor： PAHL WOLFGANG

IPC: B81C1/00

CPC classification number: B81C1/00825 ,  B81B7/0058 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2207/012 ,  B81B2207/115 ,  B81C2201/053 ,  B81C2203/0785 ,  H01L2224/16225 ,  H01L2224/48137 ,  H01L2224/73257 ,  H01L2924/16151 ,  H01L2924/16152

Abstract: For producing a structured coating, or for removing a coating from a sensitive region in a gentle manner, a release film is applied under the coating in the region not to be coated and is structured. In a release step, the adhesion force acting upon the release film is reduced and the release film is lifted off together with the coating applied on top.

Abstract translation: 为了产生图案化的涂层，或用于轻轻提起之上的涂层的感光区域，它在被提出的非施加涂层和结构下被涂覆在剥离膜。 在释放步骤中，将剥离薄膜没有在区域减小到被涂覆在粘合并随后与上述施加的涂层一起剥离。

公开(公告)号：WO2013061313A1

公开(公告)日：2013-05-02

申请号：PCT/IB2012/055982

申请日：2012-10-29

Applicant: STMICROELECTRONICS S.R.L.

Inventor： LOSA, Stefano ,  PEZZUTO, Raffaella ,  CAMPEDELLI, Roberto ,  AZPEITIA URQUIA, Mikel ,  PERLETTI, Matteo ,  ESPOSITO, Luigi

IPC: B81C1/00

CPC classification number: H01L21/02178 ,  B81B7/0032 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81C1/00595 ,  B81C1/00801 ,  B81C2201/014 ,  B81C2201/053 ,  H01L21/0228

Abstract: A method for manufacturing a protective layer (25) for protecting an intermediate structural layer (22) against etching with hydrofluoric acid (HP), the intermediate structural layer (22) being made of a material that can be etched or damaged by hydrofluoric acid, the method comprising the steps of: forming a first layer of aluminium oxide, by atomic layer deposition, on the intermediate structural layer (22); performing a thermal crystallization process on the first layer of aluminium oxide, forming a first intermediate protective layer (25a),- forming a second layer of aluminium oxide, by atomic layer deposition, above the first intermediate protective layer; and performing a thermal crystallisation process on the second layer of aluminium oxide, forming a second intermediate protective layer (25b) and thereby completing the formation of the protective layer (25). The method for forming the protective layer (25) can be used, for example, during the manufacturing steps of an inertial sensor such as a gyroscope or an accelerometer.

Abstract translation: 一种用于制造用于保护中间结构层（22）以防止用氢氟酸（HP）蚀刻的保护层（25）的方法，所述中间结构层（22）由可被氢氟酸蚀刻或损坏的材料制成， 该方法包括以下步骤：通过原子层沉积在中间结构层（22）上形成第一氧化铝层; 在第一氧化铝层上进行热结晶处理，形成第一中间保护层（25a）， - 通过原子层沉积形成第二层氧化铝，在第一中间保护层上方; 以及对所述第二氧化铝层进行热结晶处理，形成第二中间保护层（25b），从而完成所述保护层（25）的形成。 形成保护层（25）的方法可以用于例如陀螺仪或加速度计等惯性传感器的制造步骤。

公开(公告)号：WO2011022087A1

公开(公告)日：2011-02-24

申请号：PCT/US2010/027937

申请日：2010-03-19

Applicant: BREWER SCIENCE INC. ,  TANG, Tingji ,  XU, Gu ,  ZHONG, Xing-Fu ,  HONG, Wenbin ,  FLAIM, Tony, D. ,  YESS, Kimberly

Inventor： TANG, Tingji ,  XU, Gu ,  ZHONG, Xing-Fu ,  HONG, Wenbin ,  FLAIM, Tony, D. ,  YESS, Kimberly

IPC: H01L21/312

CPC classification number: B81C1/00801 ,  B81C2201/053 ,  C08G61/08 ,  C08G2261/3324 ,  C08G2261/418 ,  G03F7/033 ,  G03F7/094 ,  H01L21/0274 ,  H01L21/3081 ,  Y10T428/31645 ,  Y10T428/31667 ,  Y10T428/31692 ,  Y10T428/31855 ,  Y10T428/31909

Abstract: New compositions and methods of using those compositions as protective layers during the production of semiconductor and MEMS devices are provided. The compositions comprise a cycloolefin copolymer dispersed or dissolved in a solvent system, and can be used to form layers that protect a substrate during acid etching and other processing and handling. The protective layer can be photosensitive or non-photosensitive, and can be used with or without a primer layer beneath the protective layer. Preferred primer layers comprise a basic polymer in a solvent system.

Abstract translation: 提供了在制造半导体和MEMS器件期间使用这些组合物作为保护层的新组合物和方法。 组合物包含分散或溶解在溶剂体系中的环烯烃共聚物，并且可以用于在酸蚀刻和其它加工和处理期间形成保护基材的层。 保护层可以是光敏的或非感光的，并且可以在保护层下面使用或不使用底漆层。 优选的底漆层在溶剂体系中包含碱性聚合物。

公开(公告)号：WO2007113300A1

公开(公告)日：2007-10-11

申请号：PCT/EP2007/053244

申请日：2007-04-03

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ,  CHARLET, Barbara ,  LE POCHE, Hélène ,  GOBIL, Yveline

Inventor： CHARLET, Barbara ,  LE POCHE, Hélène ,  GOBIL, Yveline

IPC: B81C1/00

CPC classification number: B81C1/00833 ,  B81B2203/0315 ,  B81C2201/019 ,  B81C2201/053 ,  H01J9/025

Abstract: L'invention concerne un procédé de protection de l'intérieur d'au moins une cavité (4) présentant une partie d'intérêt (5) et débouchant sur une face d'un élément microstructuré (1), consistant à déposer sur ladite face une couche non conforme (6) d'un matériau de protection, ladite couche non-conforme bouchant la cavité sans recouvrir la partie d'intérêt. L'invention concerne également un procédé de fabrication d'un dispositif comportant un tel élément microstructuré.

Abstract translation: 本发明涉及一种保护至少一个空腔（4）的内部的方法，该空腔具有感兴趣的部分（5）并且通向微结构元件（1）的表面上，该方法包括沉积在所述面上 保护材料的非保形层（6），所述非保形层堵塞空腔而不覆盖感兴趣的部分。 本发明还涉及一种制造包括这种微结构元件的器件的方法。