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    SOI CMOS BODY CONTACT THROUGH GATE, SELF-ALIGNED TO SOURCE-DRAIN DIFFUSIONS.
    71.
    发明专利
    SOI CMOS BODY CONTACT THROUGH GATE, SELF-ALIGNED TO SOURCE-DRAIN DIFFUSIONS. 未知

    公开(公告)号：MY121158A

    公开(公告)日：2005-12-30

    申请号：MYPI20003023

    申请日：2000-07-03

    Applicant: IBM

    Inventor： HARGROVE MICHAEL J ,  MANDELMAN JACK A

    IPC: H01L21/28 ,  H01L27/01 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

    Abstract: A STRUCTURE AND PROCESS FOR MAKING A SEMICONDUCTOR DEVICE WITH SOI BODY CONTACTS UNDER THE GATE CONDUCTOR.THE GATE CONDUCTER IS PARTITIONED INTO SEGMENTS AND PROVIDES A BODY CONTACT UNDER EACH GATE CONDUCTER SEGMENT OVER THE WIDTH OF THE DEVICE. A PLURALITY OF BODY CONTACTS MAY BE DISTRIBUTED ACROSS THE LENGTH OF THE GATE CONDUCTER.THIS RESULTS IN A RELATIVELY SHORT PATH FOR HOLES LEAVING THE BODY TO TRAVERSE AND ALLOWS ACCUMULATED CHARGE TO BE REMOVED FROM THE BODY REGION UNDER THE GATE.THE STRUCTURE PROVIDES FOR STABLE AND EFFICIENT BODY-CONTACT OPERATION FOR SOI MOSFETS OF ANY WIDTH OPERATING AT HIGH SPEEDS.FIG. 13

    72.
    发明专利
    未知

    公开(公告)号：DE10361272A1

    公开(公告)日：2004-08-05

    申请号：DE10361272

    申请日：2003-12-24

    Applicant: IBM ,  INFINEON TECHNOLOGIES AG

    Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

    IPC: H01L21/8242

    Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

    73.
    发明专利
    未知

    公开(公告)号：DE10350703B4

    公开(公告)日：2009-04-02

    申请号：DE10350703

    申请日：2003-10-30

    Applicant: IBM ,  QIMONDA AG

    Inventor： MANDELMAN JACK A ,  CHUDZIK MICHAEL ,  SEITZ MIHEL

    IPC: H01L21/8242 ,  H01L27/108 ,  H01L21/329 ,  H01L29/94

    Abstract: A memory cell includes: a trench capacitor, including a trench silicon layer having an upper portion and a lower portion, and a buried plate disposed adjacent the lower portion of the trench silicon layer; an array FET having a gate portion, a drain portion, a source portion, and a buried strap coupled to one of the source and drain portions, the buried strap being in communication with the upper portion of the trench silicon layer; and a collar disposed about the upper portion of the trench silicon layer and between the buried strap and the buried plate, the collar including a re-entrant bend that is operable to decrease an electric field between the buried strap and the buried plate.

    75.
    发明专利
    未知

    公开(公告)号：DE10344862A1

    公开(公告)日：2004-04-15

    申请号：DE10344862

    申请日：2003-09-26

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

    IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

    Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

    76.
    发明专利
    未知

    公开(公告)号：DE10310571A1

    公开(公告)日：2003-10-02

    申请号：DE10310571

    申请日：2003-03-11

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  MCSTAV KEVIN

    IPC: H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/108

    Abstract: Short channel effects in vertical MOSFET transistors are considerably reduced, junction leakage in DRAM cells is reduced and other device parameters are unaffected in a transistor having a vertically asymmetric threshold implant. A preferred embodiment has the peak of the threshold implant moved from the conventional location of midway between source and drain to a point no more than one third of the channel length below the bottom of the source.

    80.
    发明专利
    未知

    公开(公告)号：DE69934357D1

    公开(公告)日：2007-01-25

    申请号：DE69934357

    申请日：1999-06-17

    Applicant: SIEMENS AG ,  IBM

    Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  RADENS CARL J

    IPC: H01L21/8242 ,  H01L27/108

    Abstract: Trench capacitors are fabricated utilizing a method which results in a refractory metal salicide as a component of the trench electrode in a lower region of the trench. The salicide-containing trench electrode exhibits reduced series resistance compared to conventional trench electrodes of similar dimensions, thereby enabling reduced ground rule memory cell leats and/or reduced cell access time. The trench capacitors of the invention are especially useful as components of DRAM memory cells.

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