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公开(公告)号:DE10130978C2
公开(公告)日:2003-09-25
申请号:DE10130978
申请日:2001-06-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HELMUT , ZIMMERMANN ELLEN
IPC: G11C29/00
Abstract: A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p-k locations of the pattern are unoccupied.
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公开(公告)号:DE10137697C2
公开(公告)日:2003-06-18
申请号:DE10137697
申请日:2001-08-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor: MORGAN ALAN , FISCHER HELMUT
IPC: G01R31/3193 , G01R31/3177 , G01R31/3187 , H01L21/66
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公开(公告)号:DE10208611A1
公开(公告)日:2003-05-22
申请号:DE10208611
申请日:2002-02-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SOMMER MICHAEL , FISCHER HELMUT , ZUCKERSTAETTER ANDREA
IPC: G11C11/406 , G11C11/408
Abstract: The digital memory or dynamic random access memory (DRAM) device has a refresh control device (13a-13f,14) that is designed to carry out a refresh cycle in the form of successive sub-cycles, whereby in at least one of these sub-cycles word lines of at least two non-adjacent segments in each segment group are sequentially activated simultaneously.
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公开(公告)号:DE10149099A1
公开(公告)日:2003-04-24
申请号:DE10149099
申请日:2001-10-05
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PFEIFFER JOHANN , FISCHER HELMUT
IPC: G11C7/12 , G11C7/18 , G11C11/4094 , G11C11/4097
Abstract: Each line circuit breaker (LS) has switching devices for sensing electrical potential in a pair of wires in each of the two-wire local and master data lines (LD,MD). The line circuit breaker transfers the logic potential to associated one of the pair of wires in master and local data lines, when one of the wires in the local and master data lines is at the logic potential, respectively.
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公开(公告)号:DE10143033A1
公开(公告)日:2003-04-03
申请号:DE10143033
申请日:2001-09-01
Applicant: INFINEON TECHNOLOGIES AG
Inventor: PFEIFFER JOHANN , FISCHER HELMUT , KLEHN BERND
IPC: G11C11/4076 , G11C11/4097 , G11C11/407 , G11C7/22
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公开(公告)号:DE10128254A1
公开(公告)日:2003-03-06
申请号:DE10128254
申请日:2001-06-11
Applicant: INFINEON TECHNOLOGIES AG
Inventor: KUHNE SEBASTIAN , FISCHER HELMUT , KLEHN BERND , BENEDIX ALEXANDER , SCHNEIDER HELMUT
IPC: G11C8/14 , G11C11/408 , G11C5/06
Abstract: An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.
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公开(公告)号:DE10120672A1
公开(公告)日:2002-11-07
申请号:DE10120672
申请日:2001-04-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HELMUT , CHRISSOSTOMIDIS IOANNIS
IPC: G11C7/10 , G11C11/412
Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.
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公开(公告)号:DE10107314A1
公开(公告)日:2002-09-05
申请号:DE10107314
申请日:2001-02-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor: SZCZYPINSKI KAZIMIERZ , FISCHER HELMUT
IPC: G11C7/06 , G11C11/409 , G11C11/401 , G11C7/12
Abstract: The invention relates to a semiconductor memory wherein the substantially parallel bit lines (38, 39) are capacitatively coupled with one another. Outer sections (13, 14, 36, 37) of said bit lines are linked with an interposed sense amplifier (10) via respective switches (27, 28, 29, 30). The aim of the invention is to keep to a minimum the capacitative coupling of other bit lines into the bit line (39) not coupled to the memory cell (15) to be read out during read-out of a memory cell (15) before the sense amplifier (10) starts amplification. To this end, the switches (28, 29) in said bit line (39) are in the position in which they are conducting. During the amplification phase the remote outer section (37) of said bit line (39) is switched off via the respective switch (29). In an embodiment of the invention, the capacity of the bit line (39) linked with the memory cell (15) to be read out is increased even further by additionally activating a precharge circuit (31).
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公开(公告)号:DE10021776C2
公开(公告)日:2002-07-18
申请号:DE10021776
申请日:2000-05-04
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HELMUT , SCHNEIDER HELMUT , SCHOENINGER SABINE , MARKERT MICHAEL
IPC: G11C7/06 , G11C11/4091
Abstract: At least one of the drive transistors (N1, P1) is arranged with its doping areas between the associated NMOS or PMOS transistors of the read/write amplifiers (N2, N3, P2, P3), and the gate of these drive transistors (N1, P1) is constructed as a two-strip gate (N111, P111).
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公开(公告)号:DE10055920A1
公开(公告)日:2002-05-23
申请号:DE10055920
申请日:2000-11-10
Applicant: INFINEON TECHNOLOGIES AG
Inventor: FISCHER HELMUT , SCHNABEL JOACHIM
IPC: G11C8/08 , G11C11/4074
Abstract: The memory has a line decoder (4) for activating word lines, connected to an address line for transferring address signals. A voltage regulator circuit (5) has a connection for a supply voltage to be regulated, for application to one of the word lines. A drive circuit (3) sets the supply voltage, and is connectable to the address lines and the voltage regulator circuit.
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