71.
    发明专利
    未知

    公开(公告)号:DE10130978C2

    公开(公告)日:2003-09-25

    申请号:DE10130978

    申请日:2001-06-27

    Abstract: A RAM circuit has a memory cell array whose number of rows is an integer multiple of an integer p>1 and is composed of regular and redundant rows. Each row is assigned a driver. The space occupied by the cell array and by the drivers is subdivided into two sections, in each of which there is situated a subset of the regular rows and a subset of the redundant rows. In the first section, the number of rows is by a number k smaller than an integer multiple of p. In each section, each driver occupies a location allocated to it in a regular two-dimensional pattern of locations, each of which has one of p possible X coordinates in the row direction. The locations of the pattern are occupied without any vacancies within the first section, and, within the second section, p-k locations of the pattern are unoccupied.

    76.
    发明专利
    未知

    公开(公告)号:DE10128254A1

    公开(公告)日:2003-03-06

    申请号:DE10128254

    申请日:2001-06-11

    Abstract: An integrated memory has a memory cell array, which is subdivided into a plurality of separate segments. A first and a second local word line in different segments together form a common global word line. The global word line is decoded via a row decoder. The first and second local word lines are connected to a column decoder in such a way that they can be decoded individually and segment by segment in a manner dependent on a column address. The memory thus allows fast and current-saving activation of a word line.

    77.
    发明专利
    未知

    公开(公告)号:DE10120672A1

    公开(公告)日:2002-11-07

    申请号:DE10120672

    申请日:2001-04-27

    Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.

    78.
    发明专利
    未知

    公开(公告)号:DE10107314A1

    公开(公告)日:2002-09-05

    申请号:DE10107314

    申请日:2001-02-16

    Abstract: The invention relates to a semiconductor memory wherein the substantially parallel bit lines (38, 39) are capacitatively coupled with one another. Outer sections (13, 14, 36, 37) of said bit lines are linked with an interposed sense amplifier (10) via respective switches (27, 28, 29, 30). The aim of the invention is to keep to a minimum the capacitative coupling of other bit lines into the bit line (39) not coupled to the memory cell (15) to be read out during read-out of a memory cell (15) before the sense amplifier (10) starts amplification. To this end, the switches (28, 29) in said bit line (39) are in the position in which they are conducting. During the amplification phase the remote outer section (37) of said bit line (39) is switched off via the respective switch (29). In an embodiment of the invention, the capacity of the bit line (39) linked with the memory cell (15) to be read out is increased even further by additionally activating a precharge circuit (31).

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