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    Process for making semiconductor acceleration sensor having anti-etching layer
    71.
    发明授权
    Process for making semiconductor acceleration sensor having anti-etching layer 失效
    具有防腐蚀层的半导体加速度传感器的制造方法

    公开(公告)号：US5395802A

    公开(公告)日：1995-03-07

    申请号：US37335

    申请日：1993-03-26

    Applicant: Shigeyuki Kiyota ,  Hideo Muro

    Inventor： Shigeyuki Kiyota ,  Hideo Muro

    IPC: B81B3/00 ,  G01P15/08 ,  G01P15/12 ,  H01L29/84 ,  H01L21/465

    CPC classification number: B81C1/00666 ,  B81C1/00595 ,  G01P15/0802 ,  G01P15/123 ,  B81B2201/0235 ,  B81B2203/0118 ,  B81B2203/0315 ,  B81C2201/014 ,  B81C2201/0177 ,  G01P2015/0828 ,  Y10S438/924

    Abstract: A semiconductor acceleration transducer is fabricated so that the semiconductor beam and the piezoelectric transducing element are accurately positioned relative to each other, and the impact resistance is improved. The fabrication process comprises a wafer preparing step for forming a buried layer between a substrate of a first conductivity type and an epitaxial layer of a second conductivity type, a doping step for forming a diffusion region of the first conductivity type in the epitaxial layer, and an etching step for removing unwanted portions of the substrate and the diffusion region from the bottom of the substrate to shape the beam supporting portion serving as a seismic mass. The buried layer is formed at such a position that the shape and position of the beam is determined by the buried layer. The buried layer may be a second conductivity type layer to determine the contour of the beam by stopping the etching process or may be a first conductivity type layer which is etched away to determine the contour of the beam with its diffusion contour.

    Abstract translation: 制造半导体加速度传感器，使得半导体束和压电换能元件相对于彼此精确地定位，并且提高了抗冲击性。 制造工艺包括用于在第一导电类型的衬底和第二导电类型的外延层之间形成掩埋层的晶片准备步骤，用于在外延层中形成第一导电类型的扩散区域的掺杂步骤，以及 蚀刻步骤，用于从衬底的底部除去衬底和扩散区的不需要的部分，以形成用作抗震质量的梁支撑部分。 掩埋层形成在这样的位置，即由掩埋层决定光束的形状和位置。 掩埋层可以是第二导电类型层，以通过停止蚀刻工艺来确定光束的轮廓，或者可以是蚀刻掉的第一导电类型层，以确定具有其扩散轮廓的光束的轮廓。

    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY
    75.
    发明公开
    METHOD OF FORMING SEMICONDUCTOR DEVICES THROUGH EPITAXY 审中-公开
    法通过外延半导体器件的

    公开(公告)号：EP1578685A2

    公开(公告)日：2005-09-28

    申请号：EP03777831.3

    申请日：2003-10-23

    Applicant: Freescale Semiconductor Inc.

    Inventor： GOGOI, Bishnu

    IPC: B81B3/00 ,  B81C1/00

    CPC classification number: B81B3/001 ,  B81C2201/0109 ,  B81C2201/0177

    Abstract: A method for creating a semiconductor structure is provided. In accordance with the method, a semiconductor substrate (101) is provided over which is disposed a sacrificial layer (103), and which has a thin single crystal semiconductor layer (105) disposed over the sacrificial layer (103). An opening (107) is then created which extends through the semiconductor layer (105) and into the sacrificial layer (103). The semiconductor layer (105) is then epitaxially grown to a suitable device thickness, thereby resulting in a device layer. The semiconductor layer is grown such that the resulting device layer extends over the opening (107), and such that the surface of the portion of the device layer extending over the opening is single crystal silicon.

    Method for manufacturing integrated structures including removing a sacrificial region
    76.
    发明公开
    Method for manufacturing integrated structures including removing a sacrificial region 失效
    用于制造包括去除牺牲区域的集成结构的方法

    公开(公告)号：EP0922944A2

    公开(公告)日：1999-06-16

    申请号：EP98830266.7

    申请日：1998-04-30

    Applicant: STMicroelectronics S.r.l.

    Inventor： Montanini, Pietro ,  Ferrera, Marco ,  Castoldi, Laura ,  Gelmi, Ilaria

    IPC: G01L9/00

    CPC classification number: B81C1/00476 ,  B81B2203/033 ,  B81C1/00801 ,  B81C2201/0177 ,  B81C2201/053 ,  G01C19/56 ,  G01P15/0802 ,  G01P15/097 ,  G01P15/125 ,  H01L21/76202 ,  H01L21/764

    Abstract: The method is based on the use of a silicon carbide mask for removing a sacrificial region. In case of manufacture of integrated semiconductor material structures, the following steps are performed: forming a sacrificial region (6) of silicon oxide on a substrate (1) of semiconductor material; growing a pseudo-epitaxial layer (8); forming an electronic circuit (10-13, 18); depositing a silicon carbide layer (21); defining photolithographycally the silicon carbon layer so as to form an etching mask (23) containing the topography of a microstructure (27) to be formed; with the etching mask (23), forming trenches (25) in the pseudo-epitaxial layer (8) as far as the sacrificial region (6) so as to laterally define the microstructure; and removing the sacrificial region (6) through the trenches (25).

    Abstract translation: 该方法基于使用碳化硅掩模去除牺牲区域。 在制造集成半导体材料结构的情况下，执行以下步骤：在半导体材料的衬底（1）上形成氧化硅的牺牲区域（6） 生长伪外延层（8）; 形成电子电路（10-13,18）; 沉积碳化硅层（21）; 定义光刻硅碳层以形成包含待形成的微结构（27）的形貌的蚀刻掩模（23） 利用蚀刻掩模（23），在伪外延层（8）中形成直至牺牲区域（6）的沟槽（25）以横向地限定微结构; 并通过沟槽（25）去除牺牲区域（6）。

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