公开(公告)号：KR101705726B1

公开(公告)日：2017-02-13

申请号：KR1020120152409

申请日：2012-12-24

Applicant: 한국전자통신연구원

Inventor： 배성범 ,  김성복 ,  문재경 ,  남은수

IPC: H01L21/02 ,  H01L21/32

CPC classification number: H01L21/0254 ,  H01L21/02458 ,  H01L21/02496 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/32

Abstract: 본발명은반도체기판의제조방법을개시한다. 그의방법은, 기판의가장자리를둘러싸는차단패턴을형성하는단계와, 상기차단패턴을제외한상기기판의전면에이완층을형성하는단계와, 상기이완층 및상기차단패턴상에에피반도체층을형성하는단계를포함한다. 여기서, 상기에피반도체층은상기차단패턴상에서부터성장되지않고, 상기이완층의측벽및 상부에등방적으로성장되는선택적등방성성장방법에의해상기차단패턴을점진적으로덮을수 있다.

Abstract translation: 本发明构思提供了制造半导体衬底的方法。 该方法可以包括形成围绕衬底的边缘的停止图案，在除了停止图案之外的基板的整个顶表面上形成过渡层，以及在过渡层和停止图案上形成外延半导体层。 外延半导体层可能不会从停止图案生长。 也就是说，外延半导体层可以通过选择性各向同性生长方法从过渡层的顶表面和侧壁各向同性地生长，使得外延半导体层可以逐渐覆盖停止图案。

公开(公告)号：KR101695708B1

公开(公告)日：2017-01-13

申请号：KR1020140002913

申请日：2014-01-09

Applicant: 한국전자통신연구원

Inventor： 전치훈 ,  고상춘 ,  문석환 ,  장우진 ,  배성범 ,  박영락 ,  나제호 ,  문재경 ,  남은수

IPC: H01L23/473 ,  H01L21/3205

CPC classification number: H01L21/3065 ,  H01L21/3081 ,  H01L21/32051 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: 본발명은반도체소자및 그제조방법을제공한다. 이반도체소자는기판상에제공된활성영역, 상기기판의일측에매립된단일공동으로구성된유입채널, 상기기판의타측에매립된단일공동으로구성된유출채널, 상기기판에매립된다수의공동들로구성되며일단은상기유입채널의측면에연결되고타단은상기유출채널의측면에연결되는복수개의마이크로채널들을포함하는마이크로채널어레이, 및상기마이크로채널들을이격시켜구분하는마이크로히트싱크어레이를포함할수 있다.

Abstract translation: 提供半导体器件及其制造方法。 半导体器件包括：设置在衬底上的有源区; 入口通道形成为隐藏在所述基板的一侧中的单个空腔; 出口通道形成为埋在基板的另一侧中的单个腔; 微通道阵列，其包括多个微通道，其中所述多个微通道形成为埋在所述衬底中的多个空腔，并且所述微通道阵列的一端连接到所述入口通道的一侧，而另一端 的微通道阵列连接到出口通道的一侧; 以及将微通道彼此分离的微型散热器阵列。

公开(公告)号：KR101616157B1

公开(公告)日：2016-04-27

申请号：KR1020120077726

申请日：2012-07-17

Applicant: 한국전자통신연구원

Inventor： 장우진 ,  임종원 ,  안호균 ,  고상춘 ,  배성범 ,  주철원 ,  박영락 ,  문재경 ,  남은수

IPC: H01L29/78 ,  H01L21/336

Abstract: 게이트전극과드레인전극사이에형성되는필드플레이트를통해소자의항복전압을높이는동시에제조공정을더욱용이하게할 수있는전력반도체소자및 그제조방법을제공한다. 본발명의일 실시예에의한전력반도체소자는, 기판상에형성되는소스전극과드레인전극, 상기소스전극과상기드레인전극사이에상기두 전극보다낮은높이로형성되며, 상기기판이노출되는식각부를포함하는유전층, 상기식각부상에형성되는게이트전극, 상기게이트전극과상기드레인전극사이의유전층상에형성되는필드플레이트및 상기필드플레이트와상기소스전극을연결하는메탈을포함한다.

公开(公告)号：KR101596079B1

公开(公告)日：2016-02-22

申请号：KR1020120062664

申请日：2012-06-12

Applicant: 한국전자통신연구원

Inventor： 안호균 ,  임종원 ,  배성범 ,  고상춘 ,  박영락 ,  장우진 ,  문재경 ,  남은수 ,  김정진 ,  주철원

IPC: H01L21/336 ,  H01L29/78

Abstract: 별도의리소그라피공정과그에따른추가적인공정단계없이전계전극을형성함으로써제조비용을낮추고소자의안정성및 생산성을향상시킬수 있는전계효과트랜지스터및 그제조방법을제공한다. 본발명의일 실시예에의한전계효과트랜지스터의제조방법은, 기판상에활성층, 캡층, 오믹금속층및 절연막을순차적으로형성하는단계; 상기절연막상에다층의감광막을형성하는단계; 상기다층의감광막을패터닝하여게이트전극을위한제 1 개구부및 전계전극을위한제 2 개구부를포함하는감광막패턴을형성하는단계; 상기감광막패턴을식각마스크로이용하여상기절연막을식각하되, 상기제 1 개구부를통해상기캡층이노출되도록상기제 1 개구부내의절연막을더욱깊게식각하는단계; 상기제 1 개구부를통해절연막이식각되어노출된캡층을식각하여게이트리쎄스영역을형성하는단계; 및상기게이트리쎄스영역과, 상기식각된절연막상에금속을증착하여게이트-전계전극층을형성하는단계를포함한다.

公开(公告)号：KR1020150077737A

公开(公告)日：2015-07-08

申请号：KR1020130166516

申请日：2013-12-30

Applicant: 한국전자통신연구원

Inventor： 고상춘 ,  문재경 ,  장우진 ,  배성범 ,  박영락 ,  전치훈 ,  문석환 ,  장우영 ,  김정진 ,  장현규 ,  나제호 ,  남은수

IPC: H01L29/66 ,  H01L29/47 ,  H01L21/02 ,  H01L21/283 ,  H01L21/321 ,  H01L29/20 ,  H01L29/778

CPC classification number: H01L21/3212 ,  H01L21/0254 ,  H01L21/283 ,  H01L21/28575 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/452 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/475 ,  H01L29/778

Abstract: 본발명의질화물반도체소자의제조방법에관한것으로제 1 및제 2 질화물반도체층들이차례로적층된성장기판상에복수의전극들을형성하는것, 상기각각의전극들상에상부금속층들을형성하는것, 상기성장기판을제거하여상기제 1 질화물반도체층의하면을노출하는것 및상기노출된제 1 질화물반도체층의하면상에제 3 질화물반도체층및 하부금속층을차례로형성하는것을포함하는질화물반도체소자의제조방법이제공된다.

Abstract translation: 本发明涉及一种制造氮化物半导体器件的方法。 提供了一种制造氮化物半导体器件的方法，其包括在生长衬底上形成电极，其中连续堆叠第一和第二氮化物半导体层，在每个电极上形成上部金属层，将第一氮化物半导体层的下表面暴露于第一氮化物半导体层的下表面 去除生长衬底，以及在暴露的第一氮化物半导体层的下表面上形成第三氮化物半导体层和下金属层。

公开(公告)号：KR1020140091093A

公开(公告)日：2014-07-21

申请号：KR1020120152409

申请日：2012-12-24

Applicant: 한국전자통신연구원

Inventor： 배성범 ,  김성복 ,  문재경 ,  남은수

IPC: H01L21/02 ,  H01L21/32

CPC classification number: H01L21/0254 ,  H01L21/02458 ,  H01L21/02496 ,  H01L21/0262 ,  H01L21/02664 ,  H01L21/32 ,  H01L21/02389

Abstract: Disclosed is a method for manufacturing a semiconductor substrate. The method includes a step of forming a blocking pattern which surrounds the edge of a substrate, a step of forming a relaxation layer on the front surface of the substrate except for the blocking pattern, and a step of forming an epi semiconductor layer on the blocking pattern and the relaxation layer. Here, the epi semiconductor layer is not grown on the blocking pattern and gradually covers the blocking pattern by a selective isotropy growth method by which the epi semiconductor layer is isotropically grown on the sidewall and the upper part of the relaxation layer.

Abstract translation: 公开了半导体基板的制造方法。 该方法包括形成围绕衬底边缘的阻挡图案的步骤，除了阻挡图案之外在衬底的前表面上形成弛豫层的步骤，以及在阻挡层上形成外延半导体层的步骤 图案和松弛层。 这里，外延半导体层不是在阻挡图案上生长，并且通过选择性各向同性生长方法逐渐覆盖阻挡图案，通过该方法，外延半导体层在弛豫层的侧壁和上部上各向同性地生长。

公开(公告)号：KR1020140080750A

公开(公告)日：2014-07-01

申请号：KR1020120146827

申请日：2012-12-14

Applicant: 한국전자통신연구원

Inventor： 주철원 ,  윤형섭 ,  임종원 ,  이상흥 ,  김성일 ,  강동민 ,  남은수 ,  문재경

IPC: G01R31/26

CPC classification number: G01R1/0466 ,  G01R1/0458

Abstract: According to an embodiment of the present invention, a semiconductor device testing apparatus comprises a first socket accommodating a package on which a semiconductor device to be tested is mounted; and a second socket coupled to the first socket. The first socket includes an upper part having a hole accommodating the package and a terminal pad formed at both side ends of the hole to hold input and output terminals of the package; and a lower part having a heating room, which accommodates a heater to heat the semiconductor device, and a temperature sensing part for measuring the temperature of the semiconductor device in the heating room. The second socket comprises a probe card with a pattern to receive a test signal from an external power source.

Abstract translation: 根据本发明的一个实施例，一种半导体器件测试装置包括容纳封装的第一插座，其上安装有要测试的半导体器件; 以及耦合到第一插座的第二插座。 第一插座包括具有容纳封装的孔的上部和形成在孔的两个侧端处以保持封装的输入和输出端子的端子焊盘; 以及具有加热室的下部，其容纳用于加热半导体器件的加热器，以及用于测量加热室中的半导体器件的温度的温度检测部。 第二插座包括具有从外部电源接收测试信号的模式的探针卡。

公开(公告)号：KR1020140080574A

公开(公告)日：2014-07-01

申请号：KR1020120144126

申请日：2012-12-12

Applicant: 한국전자통신연구원

Inventor： 윤형섭 ,  민병규 ,  임종원 ,  안호균 ,  김성일 ,  이상흥 ,  강동민 ,  주철원 ,  문재경

IPC: H01L29/778 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L29/20 ,  H01L21/285 ,  H01L21/28 ,  H01L29/201

CPC classification number: H01L29/66462 ,  H01L21/02118 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/0254 ,  H01L21/28264 ,  H01L21/28593 ,  H01L21/31111 ,  H01L21/31144 ,  H01L29/2003 ,  H01L29/201 ,  H01L29/205 ,  H01L29/404 ,  H01L29/42316 ,  H01L29/42376 ,  H01L29/778 ,  H01L29/7786

Abstract: Provided is a field effect transistor. The transistor includes a capping layer provided on a substrate; source and drain ohmic electrodes spaced apart from each other on the capping layer; first and second insulating layers sequentially laminated on the capping layer to cover the source and drain ohmic electrodes; a Γ-shaped gate electrode including a leg part passing through the second insulating layer, the first insulating layer, and the capping layer and connected with the substrate between the source and drain ohmic electrodes and a head part extended to the second insulating layer; a first planarization layer provided on the second insulating layer to cover the Γ-shaped gate electrode; and a first electrode passing through the first planarization layer and the second and first insulating layers, and connected with the source and drain ohmic electrodes while the being extended to the first planarization layer.

Abstract translation: 提供了场效应晶体管。 晶体管包括设置在基板上的封盖层; 源极和漏极欧姆电极在封盖层上彼此间隔开; 顺序层压在覆盖层上以覆盖源极和漏极欧姆电极的第一和第二绝缘层; Γ形栅电极，包括通过第二绝缘层的脚部，第一绝缘层和覆盖层，并且与源极和漏极欧姆电极之间的衬底连接，以及延伸到第二绝缘层的头部; 设置在所述第二绝缘层上以覆盖所述Γ形栅电极的第一平坦化层; 以及穿过第一平坦化层和第二和第一绝缘层的第一电极，并且在被延伸到第一平坦化层的同时与源极和漏极欧姆电极连接。

公开(公告)号：KR1020140076110A

公开(公告)日：2014-06-20

申请号：KR1020120144273

申请日：2012-12-12

Applicant: 한국전자통신연구원

Inventor： 고상춘 ,  문재경 ,  민병규 ,  박영락 ,  안호균 ,  김정진 ,  남은수

IPC: H01L21/78 ,  H01L21/301

CPC classification number: H01L29/808 ,  H01L21/76898 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/432 ,  H01L29/454 ,  H01L29/66462 ,  H01L29/7786

Abstract: A semiconductor device and a method for manufacturing the same are provided. The method for manufacturing the semiconductor device comprises the steps of: forming devices including a source electrode, a drain electrode and a gate electrode on a front surface of a substrate including a bulk silicon, a buried oxide layer, an active silicon, a gallium nitride layer, and an aluminum-gallium nitride layer sequentially stacked; etching a back surface of the substrate to form a via-hole penetrating the substrate and exposing a bottom surface of the source electrode; conformally forming a ground interconnection on the back surface of the substrate having the via-hole; forming a protective layer on the front surface of the substrate; and cutting the substrate to separate the devices from each other.

Abstract translation: 提供半导体器件及其制造方法。 制造半导体器件的方法包括以下步骤：在包括体硅，掩埋氧化物层，活性硅，氮化镓的衬底的前表面上形成包括源电极，漏电极和栅电极的器件 层和依次层叠的氮化铝镓层; 蚀刻所述基板的背面以形成穿透所述基板的通孔并暴露所述源电极的底表面; 在具有通孔的基板的背面上共形地形成接地互连; 在所述基板的前表面上形成保护层; 并切割基板以将装置彼此分开。

公开(公告)号：KR1020140010479A

公开(公告)日：2014-01-27

申请号：KR1020120075571

申请日：2012-07-11

Applicant: 한국전자통신연구원

Inventor： 윤형섭 ,  민병규 ,  임종원 ,  안호균 ,  이종민 ,  김성일 ,  문재경 ,  남은수

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L21/28008 ,  H01L21/28587 ,  H01L29/42316 ,  H01L29/66863

Abstract: The present invention relates to a method for manufacturing a high performance field effect type compound semiconductor device in which a leakage current is decreased and breakdown voltage is improved. The method for manufacturing field effect type compound semiconductor device comprises the following steps of: stacking an active layer and an ohmic layer on a substrate and forming a first oxide layer on the ohmic layer; forming a mesa area vertically in predetermined areas of the first oxide layer, ohmic layer, and active layer; flattening the mesa area after forming a nitride layer by depositing a nitride film on the mesa area; forming an ohmic electrode on the first oxide layer; forming a macro-gate pattern having an under-cut shaped profile by forming a second oxide layer on the semiconductor substrate on which the ohmic electrode is formed, forming a micro-gate resist pattern, and performing dry-etching for three insulating layers including the first oxide layer, nitride layer, and second oxide layer; forming a gate recess area by applying a copolymer resist over the semiconductor substrate on which the micro-gate pattern is formed and forming a head pattern of a gamma gate electrode; and forming a gamma gate electrode by depositing a refractory metal on the semiconductor substrate on which the gate recess area is formed.

Abstract translation: 本发明涉及一种制造泄漏电流降低并提高击穿电压的高性能场效应型化合物半导体器件的方法。 制造场效应型化合物半导体器件的方法包括以下步骤：在衬底上堆叠有源层和欧姆层，并在欧姆层上形成第一氧化物层; 在第一氧化物层，欧姆层和有源层的预定区域中垂直形成台面区域; 通过在台面区域上沉积氮化物膜，在形成氮化物层之后使台面区域变平; 在所述第一氧化物层上形成欧姆电极; 通过在其上形成欧姆电极的半导体衬底上形成第二氧化物层，形成具有底切形状的宏栅图形，形成微栅抗蚀剂图案，并且对包括第二氧化物层的三个绝缘层进行干法蚀刻 第一氧化物层，氮化物层和第二氧化物层; 通过在其上形成微栅极图案的半导体衬底上施加共聚物抗蚀剂并形成伽马栅电极的头部图案，形成栅极凹部区域; 以及通过在其上形成有所述栅极凹部区域的所述半导体衬底上沉积难熔金属来形成γ栅电极。