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    84.
    发明专利
    未知

    公开(公告)号：DE19963502B4

    公开(公告)日：2008-01-03

    申请号：DE19963502

    申请日：1999-12-28

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHOENIGER SABINE ,  SCHNEIDER HELMUT

    IPC: G11C7/00 ,  G11C11/407 ,  G11C7/06 ,  G11C7/10 ,  G11C8/18 ,  G11C11/408

    Abstract: An integrated-circuit circuit arrangement has storage/memory cells (MC) arranged in a storage location array and combined into addressable units with columns of bit lines (BL) and rows of word lines (WL). A decoder (10) selects a bit line (BL) which is connected to a column (bit-line) select line (11) for transmission of a column select signal (S11), and which has a connection (12) for an input signal (S12) for activating the column select signal (S11), and a connection (21) for a row (word-line) activation signal (S21) for activating a row access- signal sequence (S22,S23). The connection (12) for the decoder (10) input signal (S12) is joined to a connection (22) for at least one signal (S22) out of the row (word-line) access-signal sequence (S22,S23) which indicates with its status that the row access is concluded.

    Dynamic random access memory circuit for lower operating voltages, includes memory cell, bit line pair, selection transistor, read-out amplifier and controller
    85.
    发明专利
    Dynamic random access memory circuit for lower operating voltages, includes memory cell, bit line pair, selection transistor, read-out amplifier and controller 未知

    公开(公告)号：DE102005057788A1

    公开(公告)日：2007-06-06

    申请号：DE102005057788

    申请日：2005-12-03

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

    IPC: G11C7/06 ,  G11C11/409 ,  H01L27/108 ,  H03F3/183

    Abstract: The memory circuit includes a bit line pair (5, 6), a memory cell (2) with a memory capacitance (3) and a selection transistor (4). When activated, this (4) connects the memory capacitance to one of the bit lines, establishing a charge difference between them (5, 6). The read-out amplifier (10) has one or more transistors (11, 2, 13, 14) amplifying the charge difference. A controller (15) applies a potential to a substrate connection of the transistors (11-14); this potential is a function of the operating state of the memory circuit. The controller applies a first or second potential to the substrate, in accordance with the operating state. The read-out amplifier is activated, to apply a high potential to one bit line, and a low potential to the other. The controller is designed to apply an intermediate potential to the substrate of the transistors, at least with the read-out amplifier inactivated. This potential lies between the low and high potentials on the bit lines. It is selected such that the transistor leakage current does not exceed a given threshold, with the read-out amplifier inactive. With the selection transistor de-activated, the controller adjusts the potential of the bit line pair to a level corresponding with the intermediate potential. When the selection transistor is activated, the read-out amplifier brings the bit lines to a corresponding low or high potential during an amplification phase, and in a holding phase, it maintains the corresponding bit line potentials. The read-out amplifier includes at least one n-channel field effect transistor. Operation of this circuitry, and of implementations with additional transistors, is further detailed. An independent claim IS INCLUDED FOR the corresponding method of operation.

    86.
    发明专利
    未知

    公开(公告)号：DE10124753B4

    公开(公告)日：2006-06-08

    申请号：DE10124753

    申请日：2001-05-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

    IPC: G11C7/06

    Abstract: The invention provides a method in which a binary memory cell signal from a; least one memory cell is applied to at least one bit line pair (201t, 201b), the binary memory cell signal from the memory tell is switched through via the bit line pair (201t, 201b) to at least one sense amplifier (202), a binary output signal of the sense amplifier (202) is switched through to a local data line pair (205) as a binary intermediate signal, the binary intermediate signal on the local data line pair (205) is switched through to at least one main data line pair (208) by means of a main data line switching transistor pair (209) in a manner dependent on a row control signal fed via a row control line (210), the main data line switching transistor pair (209) being arranged in the through-plating regions formed between the memory cell arrays.

    87.
    发明专利
    未知

    公开(公告)号：DE59912971D1

    公开(公告)日：2006-02-02

    申请号：DE59912971

    申请日：1999-07-06

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHAFFROTH THILO ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

    IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3185 ,  G01R31/3187

    Abstract: An integrated circuit with BIST (built-in self-test) device (3) for carrying out a self-test of the integrated circuit (2) and includes a circuit unit (1) to be tested. One output of the BIST device (3) is connected to a contact point (4) of the circuit which serves for external contacting and which is connected to the input (In) of the circuit unit (1) to be tested. The BIST device (3) supplies a test signal (S1) to the circuit unit (1), via the contact point (4), the latter (4) being specifically connected via an input driver (D1) to the input (In) of the circuit unit (1).

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