公开(公告)号：DE10355669A1

公开(公告)日：2005-06-30

申请号：DE10355669

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  PFIRSCH FRANK

IPC: H01L29/49 ,  H01L29/78

Abstract: The transistor has a drift zone (22) and a source zone (40), and a channel zone (30) arranged between the drift and source zones such that a gate electrode (50) having a temperature range is isolated from the channel zone. A conducting channel is formed at the gate electrode based on an electron affinity difference in the channel zone, to avoid drop of threshold voltage of the electrode during rise in temperature.

公开(公告)号：DE59911769D1

公开(公告)日：2005-04-21

申请号：DE59911769

申请日：1999-08-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： AIGNER ROBERT ,  HIEROLD CHRISTOFER ,  KAPELS HERGEN ,  KOLB STEFAN ,  MAIER-SCHNEIDER DIETER ,  OPPERMANN KLAUS-GUENTER ,  TIMME HANS-JOERG ,  SCHEITER THOMAS ,  WERNER WOLFGANG

IPC: G01P15/125 ,  B81B3/00 ,  B81B7/00 ,  B81C1/00 ,  B81C3/00 ,  G01L9/00 ,  G01L9/12 ,  G01P15/08 ,  H01L29/84 ,  H04R7/10

公开(公告)号：AU2003292985A1

公开(公告)日：2004-06-18

申请号：AU2003292985

申请日：2003-11-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOSE HELMUT ,  MIKOLAJICK THOMAS ,  WERNER WOLFGANG

IPC: H01L27/24 ,  H01L45/00 ,  H01L27/00

Abstract: A semiconductor memory device with a phase transformation memory effect includes at least one memory element in a semiconductor substrate, and a cavity arrangement including at least one cavity in spatial proximity to the respective memory element. The cavity is in spatial arrangement with the respective memory element so as to reduce thermal coupling of the respective memory element to the areas surrounding the memory element, which also reduces the thermal conductivity between memory element and the areas surrounding the memory element.

公开(公告)号：DE10124115A1

公开(公告)日：2003-02-13

申请号：DE10124115

申请日：2001-05-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  HIRLER FRANZ

IPC: H01L27/07 ,  H01L29/417 ,  H01L29/423 ,  H01L29/78

Abstract: The arrangement has a gate electrode (40) arranged in a trench extending in vertical direction of semiconductor surface (100). The gate electrode is insulated from the semiconductor surface and a source electrode (60). A Schottky diode connected in parallel with a drain-source path of the MOS transistor, is formed by the Schottky contact between source electrode and drift zone (12) of semiconductor surface.

公开(公告)号：DE10126147A1

公开(公告)日：2002-12-19

申请号：DE10126147

申请日：2001-05-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG

IPC: H01L29/786 ,  H01L29/78

Abstract: A semiconductor component is described which is realized on an insulation layer and has a first zone of a first conductivity type, a second zone of the first conduction type, and a third zone of a second conductivity type. The third zone is formed between the first zone and the second zone. A heavily doped zone of the second conductivity type is formed adjacent to the first zone and forms a tunnel diode with the first zone.

公开(公告)号：DE10014660C2

公开(公告)日：2002-08-29

申请号：DE10014660

申请日：2000-03-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  HIRLER FRANZ

IPC: H01L21/764 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417 ,  H01L29/51 ,  H01L29/78

Abstract: The semiconducting arrangement has at least two rigid electrodes (6) that are electrically separated by an insulating arrangement consisting of at least one insulating or holding coating and/or a pn junction. The insulating arrangement also contains at least one hollow vol. (7).

公开(公告)号：DE10061529A1

公开(公告)日：2002-06-27

申请号：DE10061529

申请日：2000-12-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FINK CHRISTOPH ,  HANSCH WALTER ,  EISELE IGNAZ ,  WERNER WOLFGANG

IPC: H01L21/336 ,  H01L29/10 ,  H01L29/36 ,  H01L29/78

Abstract: Semiconductor component arranged in a semiconductor body comprises a source zone (4) and a drain zone (5) both having first conductivity; a body zone (8) of second conductivity arranged between the source and drain zones; and a gate electrode (11) insulated from the semiconductor body via a dielectric (10). Regions (12', 12'', 13) in a channel zone (12) of the body zone are provided with second conductivity, the first region (13) having a doping concentration which is lower than that of the second region (12', 12''). The combination of the regions produces a threshold voltage of the component which is larger than zero. An Independent claim is also included for a process for the production of a doping layer in a vertical semiconductor component comprising applying an epitaxial layer on a semiconductor body using thermal deposition; interrupting the thermal deposition; vaporizing a thin doping layer of second conductivity after cooling the semiconductor body; and applying a further epitaxial layer to the doping layer.

公开(公告)号：DE10007415A1

公开(公告)日：2001-09-06

申请号：DE10007415

申请日：2000-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  HIRLER FRANZ

IPC: H01L29/06 ,  H01L29/40 ,  H01L29/78

Abstract: The semiconductor has a planar power switching cell with a lateral channel region (45a,45b) and an applied gate structure (50a,50b) between front and rear electrodes (S,D), with a vertical trench electrode (90a,90b) coupled to the front electrode potential on the outside of the channel region. The vertical trench electrode is provided by forming a trench in the surface of the semiconductor substrate, with the trench walls covered by a dielectric (80a,80b) before the trench is filled with a conductive material.

公开(公告)号：DE10006519A1

公开(公告)日：2001-08-23

申请号：DE10006519

申请日：2000-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： TIHANYI JENOE ,  WERNER WOLFGANG

IPC: H01L27/07 ,  H03K17/0814 ,  H03K17/687 ,  H03K17/695 ,  H01L27/088 ,  H01L23/60 ,  H03K17/64

Abstract: A driver transistor for driving a load is integrated on a substrate and includes first three (4-6) terminals, for driving the transistor (1), for connecting the load (27) to the driver transistor (1), and for connecting the transistor (1) to a reference potential, respectively. A first diode (8) is connected into circuit between the terminal well (7) and the second terminal (5), the terminal well being connected directly to the third terminal (6). A second diode (13) is connected into circuit between the second terminal (5) and the substrate. A third diode (14) is connected between the substrate and the substrate terminal in series-opposition to the second diode (13), which has high leakage current in operation in the reverse direction. The substrate terminal is specifically formed by a metal layer; the driver transistor is specifically a MOSFET, more specifically a DMOS transistor.

公开(公告)号：DE10005772A1

公开(公告)日：2001-08-23

申请号：DE10005772

申请日：2000-02-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WERNER WOLFGANG ,  TIHANYI JENOE

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/336

Abstract: A trench metal-oxide semiconductor field-effect transistor (MOSFET) has a semiconductor layer (4) placed on a semiconductor body (1,3) of one conductivity type, and is of the other conductivity type, opposite to that of the one conductivity type. A trench (5) is brought from one surface of the semiconductor layer (4) out into the semiconductor layer, and then up to the semiconductor body (1,3). A gate electrode (G) is provided in the trench (5) and is separated from the semiconductor body (1,3) and the semiconductor layer (4) by an insulating layer (6). A source- drain zone (7) of the one conductivity type is provided at the one surface in the semiconductor layer (4) and borders on the trench (5). At least one region (10) of the other conductivity type is provided in the semiconductor body (1,3) in the region of the end of the trench (5) facing opposite the one surface (of the semiconductor layer (4)).