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106 records (took 0.025 seconds)

    81.
    发明专利
    未知

    公开(公告)号：DE69627142D1

    公开(公告)日：2003-05-08

    申请号：DE69627142

    申请日：1996-08-02

    Applicant: ST MICROELECTRONICS SRL

    Inventor： GHILARDELLI ANDREA ,  CAMPARDO GIOVANNI ,  MULATTI JACOPO

    IPC: G11C5/14 ,  G11C16/06

    Abstract: A charge pump comprises at least one charge pump stage (S1-Sn) comprising a first diode (D1-Dn) having an anode (A) and a cathode (K), and a capacitor (C1-Cn) having a first plate connected to the cathode (K) of the diode (D1-Dn) and a second plate connected to a clock signal (CK1,CK2) periodically varying between a reference voltage and a supply voltage (VDD), the anode (A) of said diode (D1-Dn) forming a first terminal (NEG) of the charge pump. The charge pump comprises a second diode (Dn+1) having an anode (A) connected to the cathode (K) of the first diode (D1-Dn) and a cathode (K) forming a second terminal (POS) of the charge pump, first switching means (SW1) for selectively coupling the first terminal (NEG) of the charge pump to the voltage supply (VDD) and second switching means (SW2) for selectively coupling the second terminal (POS) of the charge pump to the reference voltage. The first switching means (SW1) and the second switching means (SW2) are respectively closed and open in a first operating condition whereby the second terminal (POS) of the charge pump acquires a voltage of the same sign but higher in absolute value than said supply voltage (VDD). The first switching means (SW1) and the second switching means (SW2) are respectively open and close in a second operating condition whereby the first terminal (NEG) of the charge pump acquires a voltage of opposite sign with respect to said voltage supply (VDD).

    82.
    发明专利
    未知

    公开(公告)号：DE69624230D1

    公开(公告)日：2002-11-14

    申请号：DE69624230

    申请日：1996-07-24

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  ZANARDI STEFANO ,  GOLLA CARLA

    IPC: H03K19/003 ,  H03K17/00

    Abstract: An output stage (1) for electronic circuits (2) with high voltage tolerance and of the type comprising an output buffer made up of a complementary transistor pair (Pu,Nu) comprising a P-channel MOS pull-up transistor (Pu) and an N-channel MOS pull-down transistor. The transistors are connected together to make up an output terminal (U) of the stage which comprises in addition a switch (6) having an input (8) connected to the output terminal (U) of the stage and an output (9) connected to the control terminal of the pull-up transistor to drive said control terminal in a state of extinction of the output buffer.

    85.
    发明专利
    未知

    公开(公告)号：ITMI20000687A1

    公开(公告)日：2001-10-01

    申请号：ITMI20000687

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COMMODARO STEFANO ,  CAMPARDO GIOVANNI ,  PICCA MASSIMILIANO ,  MONGELLI PATRIZIA

    IPC: G11C29/56

    Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

    86.
    发明专利
    未知

    公开(公告)号：DE69426818D1

    公开(公告)日：2001-04-12

    申请号：DE69426818

    申请日：1994-06-10

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CAMERLENGHI EMILIO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/34 ,  G11C29/00 ,  G11C29/04 ,  G11C29/12 ,  G11C29/50 ,  H01L27/00 ,  G06F11/20

    Abstract: Since fault phenomena such as lowering of the cell gain and cell emptying occur during normal operation the present invention proposes that in the memory device the row and/or column address decoding means (RDEC,CDEC) comprise at least one non-volatile memory (NVM) for address mapping and that the reading and writing control logic (CL) comprise means (TST) designed to identify cell faults in the rows and/or columns of the matrix (MAT) of the memory device and writing means (WM) designed to write on said non-volatile memory (NVM) during normal operation addresses corresponding to redundant rows and/or columns (RID) present in the matrix (MAT) to rectify said faults.

    87.
    发明专利
    未知

    公开(公告)号：DE69426487D1

    公开(公告)日：2001-02-01

    申请号：DE69426487

    申请日：1994-03-28

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/06 ,  G11C16/28 ,  G11C16/34

    Abstract: To reduce the supply voltage (VCC) of a nonvolatile memory (48), a read reference signal (H) is generated having a reference threshold value ranging between the maximum permissible threshold value for erased cells and the minimum permissible threshold value for written cells. To avoid reducing the maximum supply voltage, the characteristic (H) of the read reference signal is composed of two portions: a first portion (H1), ranging between the threshold value and a predetermined value (Vs), presents a slope lower than that of the characteristic (A, G) of the memory cells (50); and a second portion (H2), as of the predetermined value of the supply voltage, presents the same slope as the memory cells. The shifted-threshold, two-slope characteristic is achieved by means of virgin cells (11-13) so biased as to see bias voltages lower than the supply voltage.

    88.
    发明专利
    未知

    公开(公告)号：ITMI20000687D0

    公开(公告)日：2000-03-31

    申请号：ITMI20000687

    申请日：2000-03-31

    Applicant: ST MICROELECTRONICS SRL

    Inventor： COMMODARO STEFANO ,  CAMPARDO GIOVANNI ,  PICCA MASSIMILIANO ,  MONGELLI PATRIZIA

    IPC: G11C29/56

    Abstract: A method and control device is used for testing electronic memory devices. The method comprises loading test data and/or instructions into a control logic circuit portion associated with a matrix array of memory cells and integrated storage circuitry. According to the invention, a test operation control device is used temporarily instead of the control logic, the test operation control device being external of and connected detachably to the memory device. Advantageously, the test operation control device is a matrix cell array external of the memory.

    89.
    发明专利
    未知

    公开(公告)号：DE69325443T2

    公开(公告)日：2000-01-27

    申请号：DE69325443

    申请日：1993-03-18

    Applicant: ST MICROELECTRONICS SRL

    Inventor： CAMPARDO GIOVANNI ,  CRISENZA GIUSEPPE ,  DALLABORA MARCO

    IPC: G11C17/00 ,  G11C16/04 ,  G11C16/06 ,  G11C16/30 ,  H01L21/8247 ,  H01L27/115

    Abstract: To reduce the read and write errors caused by depleted memory array cells being turned on even when not selected, the nonselected memory cells are so biased as to present a floating terminal and a terminal at a positive voltage with respect to the substrate region. In this way, the threshold voltage of the above cells (the minimum voltage between the gate and source terminals for the cell to be turned on) increases due to the "body effect", whereby the threshold voltage depends, among other things, on the voltage drop between the cell terminal operating as the source and the substrate, and increases alongside an increase in the voltage drop.

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