中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

53 records (took 0.026 seconds)

    종형 성막 장치, 그의 사용 방법 및 기억 매체
    6.
    发明公开
    종형 성막 장치, 그의 사용 방법 및 기억 매체 有权
    垂直膜形成装置，使用它们的方法和储存介质

    公开(公告)号：KR1020110059539A

    公开(公告)日：2011-06-02

    申请号：KR1020100116850

    申请日：2010-11-23

    Applicant: 도쿄엘렉트론가부시키가이샤

    Inventor： 마츠나가마사노부 ,  초우파오화 ,  요네자와마사토 ,  하세가와마사유키 ,  하세베카즈히데

    IPC: H01L21/205

    CPC classification number: C23C16/345 ,  C23C16/4404 ,  C23C16/45542 ,  C23C16/45546

    Abstract: PURPOSE: A vertical film forming device, a using method thereof, and a storage medium are provided to reduce the Na density of SiN product layer by trapping Na in a coating layer by Cl. CONSTITUTION: A coating layer is coated on the inner wall of a process container(1). A holding member with a process agent forms a preset film on a target in the process container. First and second process gas is supplied to the process container without a plasma process in a coating process. The first and second process gas is supplied to the process container with a plasma process in a film forming process.

    Abstract translation: 目的：提供垂直成膜装置及其使用方法和存储介质，以通过Cl将Na吸收在涂层中来降低SiN产物层的Na密度。 构成：将涂层涂覆在处理容器（1）的内壁上。 具有加工剂的保持构件在处理容器中的靶上形成预设膜。 在涂布过程中，没有等离子体处理，将第一和第二工艺气体供给到处理容器。 第一和第二处理气体在成膜过程中以等离子体处理方式供应给处理容器。

    마스크 패턴의 형성 방법 및 반도체 장치의 제조 방법
    7.
    发明公开
    마스크 패턴의 형성 방법 및 반도체 장치의 제조 방법 无效
    掩模形成方法和半导体器件制造方法

    公开(公告)号：KR1020110030295A

    公开(公告)日：2011-03-23

    申请号：KR1020100072304

    申请日：2010-07-27

    Applicant: 도쿄엘렉트론가부시키가이샤

    Inventor： 나카지마시게루 ,  하세베카즈히데 ,  야에가시히데타미 ,  니시무라에이이치

    IPC: H01L21/027

    CPC classification number: H01L21/31144 ,  C23C16/26 ,  C23C16/34 ,  C23C16/45542 ,  H01J37/32082 ,  H01L21/02115 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/0337 ,  H01L21/31122 ,  H01L21/32135 ,  H01L21/0274

    Abstract: PURPOSE: A mask pattern forming method and a semiconductor device manufacturing method are provided to improve the etching process accuracy of the target etching layer by etching the target etching layer using the carbon layer having the high selectivity. CONSTITUTION: A second line part having a line width(L2) and a space width(S2) is arranged on the resist pattern(105a). The resist pattern is processed with the trimming in order to form a resist pattern(105b) consisting of the photoresist film(105). A reflection barrier layer(104) is etched with the trimmed resist pattern as the mask. A reflective barrier pattern(104a) having a line width(L3) and a space width(S3) is formed.

    Abstract translation: 目的：提供掩模图案形成方法和半导体器件制造方法，以通过使用具有高选择性的碳层蚀刻目标蚀刻层来提高目标蚀刻层的蚀刻处理精度。 构成：具有线宽（L2）和空间宽度（S2）的第二线部分布置在抗蚀剂图案（105a）上。 通过修整处理抗蚀剂图案，以形成由光致抗蚀剂膜（105）组成的抗蚀剂图案（105b）。 用修剪的抗蚀剂图案作为掩模蚀刻反射阻挡层（104）。 形成具有线宽（L3）和空间宽度（S3）的反射阻挡图案（104a）。

    반도체 장치의 제조 방법
    8.
    发明公开
    반도체 장치의 제조 방법 有权
    制造半导体器件的方法

    公开(公告)号：KR1020080106127A

    公开(公告)日：2008-12-04

    申请号：KR1020080051186

    申请日：2008-05-30

    Applicant: 도쿄엘렉트론가부시키가이샤

    Inventor： 아카사카야스시 ,  후키아게노리아키 ,  카토요시히로 ,  하세베카즈히데 ,  초우파오화

    IPC: H01L21/336

    CPC classification number: H01L21/823864 ,  H01L21/823814

    Abstract: A manufacturing method of the semiconductor device is provided to improve the operation speed and increase the operation current by removing the side wall spacer. A manufacturing method of the semiconductor device comprises the following processes: the process of forming the gate electrode(7) on the active area of semiconductor layer having the active area and the element isolation region(4); the process for forming the side wall spacer(10) on the side of the gate electrode using different material from the semiconductor layer, the element isolation region and the gate electrode; the process for introducing the impurity within the active area, and forming a pair of source and drain region(14) within the active area using the element isolation region, the gate electrode and the side wall spacer as a mask; the process of covering the gate electrode, the semiconductor layer, the element isolation region, and the side wall spacer with the metal layer(18); the process of partly making the source and drain region and the gate electrode into lower resistance.

    Abstract translation: 提供半导体器件的制造方法，以通过去除侧壁间隔物来提高操作速度并增加操作电流。 半导体器件的制造方法包括以下处理：在具有有源区域和元件隔离区域（4）的半导体层的有源区上形成栅电极（7）的工序; 使用与半导体层，元件隔离区域和栅极电极不同的材料在栅电极侧形成侧壁间隔物（10）的工艺; 用于在有源区域内引入杂质的工艺，以及使用元件隔离区域，栅极电极和侧壁间隔物作为掩模在有源区域内形成一对源极和漏极区域（14）; 用金属层（18）覆盖栅电极，半导体层，元件隔离区域和侧壁间隔物的工艺; 部分使源极和漏极区域以及栅电极成为较低电阻的过程。

Patent Agency Ranking