公开(公告)号：EP1351562B1

公开(公告)日：2010-09-01

申请号：EP03075806.4

申请日：2003-03-20

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Myers, Bruce A. ,  Tsai, Jeenhuei ,  Chengalva, Suresh K.

IPC: H05K9/00

CPC classification number: H05K5/065 ,  H05K1/0203 ,  H05K3/284 ,  H05K9/0045 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49172

公开(公告)号：EP1628345A3

公开(公告)日：2006-03-29

申请号：EP05076743.3

申请日：2005-07-28

Applicant: Delphi Technologies, Inc.

Inventor： Brandenbrug, Scott D. ,  Chengalva, Suresh K. ,  Degenkolb, Thomas A.

IPC: H01L23/473

CPC classification number: H01L23/473 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00 ,  H01L2224/0401

Abstract: An encapsulated microelectronic package includes a fluid conducting cooling tube (22) directly coupled to one or more semiconductor chips (12, 14, 16), with the encapsulant (34) being molded over the semiconductor chips (12, 14, 16) and portions of the cooling tube (22) in proximity to the semiconductor chips (12, 14, 16). The encapsulant (34) immobilizes the cooling tube (22) with respect to the semiconductor chips (12, 14, 16), and the cooling tube (22) and encapsulant (34) are designed to minimize differences in their coefficients of thermal expansion relative to the semiconductor chips (12, 14, 16).

Abstract translation: 封装的微电子封装包括直接耦合到一个或多个半导体芯片（12,14,16）的流体导电冷却管（22），其中密封剂（34）模制在半导体芯片（12,14,16）上，部分 靠近半导体芯片（12,14,16）的冷却管（22）。 密封剂（34）相对于半导体芯片（12,14,16）固定冷却管（22），并且冷却管（22）和密封剂（34）被设计成使其热膨胀系数相对较小 到半导体芯片（12,14,16）。

公开(公告)号：EP1523040B1

公开(公告)日：2018-08-29

申请号：EP04077702.1

申请日：2004-09-30

Applicant: Delphi Technologies, Inc.

Inventor： Chengalva, Suresh K. ,  Mandel, Larry M. ,  Sarma, Dwadasi H. ,  Gertiser, Kevin M. ,  Zimmerman, David W.

IPC: H01L25/065 ,  H01L23/367 ,  H01L23/427 ,  H01L23/42 ,  H01L21/48 ,  H01L21/56

CPC classification number: H01L23/427 ,  H01L21/4878 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  Y10T29/49144

Abstract: An electronic package (10) having enhanced heat dissipation is provided exhibiting dual conductive heat paths (40, 42) in opposing directions. The package (10) includes a substrate (16) having electrical conductors thereon and a flip chip (12) mounted to the substrate (16). The flip chip (12) has a first surface, solder bumps (14) on the first surface, and a second surface oppositely disposed from the first surface. The flip chip (12) is mounted to the substrate (16) such that the solder bumps (14) are registered with the conductors on the substrate (16). The package (10) further includes a stamped metal heat sink (30) in heat transfer relationship with the second surface of the flip chip (12). The heat sink (30) includes a cavity (32) formed adjacent to the flip chip (12) containing a thermally conductive material (34).

公开(公告)号：EP1628344A3

公开(公告)日：2009-09-02

申请号：EP05076730.0

申请日：2005-07-27

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Chengalva, Suresh K. ,  Degenkolb, Thomas A.

IPC: H01L23/473

CPC classification number: B29C45/14655 ,  B29C45/7207 ,  H01L23/4334 ,  H01L23/473 ,  H01L2224/16 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2224/0401

Abstract: A method of making a fluid cooled microelectronic package (10'/60') in which fluid is circulated through the package in fluid-carrying channels (40/64) defined at least in part by voids in an encapsulant (38) that surrounds the package components (12, 14, 16). Preferably, the encapsulant channels (40/64) are defined in part by heat producing components (12, 14, 16) of the package so that coolant fluid directly contacts such components. The coolant fluid can be electrically conductive or non-conductive depending on the type of components being cooled. The coolant channels (40) are formed by insert-molding a form (24) in the encapsulant (38), and removing the form (24) following the molding process. Alternately, the encapsulant is formed in two or more pieces (38a, 38b) that are joined to form the package (60'), and the coolant channels (64) are defined by recesses (62) formed in at least one of the encapsulant pieces (38a, 38b).

公开(公告)号：EP1351562A3

公开(公告)日：2005-05-11

申请号：EP03075806.4

申请日：2003-03-20

Applicant: Delphi Technologies, Inc.

Inventor： Brandenburg, Scott D. ,  Myers, Bruce A. ,  Tsai, Jeenhuei ,  Chengalva, Suresh K.

IPC: H05K9/00

CPC classification number: H05K5/065 ,  H05K1/0203 ,  H05K3/284 ,  H05K9/0045 ,  Y10T29/49117 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49171 ,  Y10T29/49172

Abstract: An overmolded electronic assembly 20 having an electromagnetic interference shield 50, in the form of a thin metal film or foil, coupled to the top of or within an overmolded body 33. The shield 50 effectively reduces the amount of electromagnetic interference ("EMI") emissions from penetrating within the assembly to the circuit board 22 without substantially increasing the cost of the unit. Thus, an electronic assembly having improved vibration, moisture, and EMI emission resistance is achieved as compared with traditional overmolded or metal assemblies. Further, because the shield 50 can be formed on the electronic assembly in one continuous processing step, a substantial savings in time and cost for the manufacturing process is also realized.

公开(公告)号：EP1523040A2

公开(公告)日：2005-04-13

申请号：EP04077702.1

申请日：2004-09-30

Applicant: Delphi Technologies, Inc.

Inventor： Chengalva, Suresh K. ,  Mandel, Larry M. ,  Sarma, Dwadasi H. ,  Gertiser, Kevin M. ,  Zimmerman, David W.

IPC: H01L25/065 ,  H01L23/367

CPC classification number: H01L23/427 ,  H01L21/4878 ,  H01L21/4882 ,  H01L21/563 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/42 ,  H01L2224/16 ,  H01L2224/73204 ,  H01L2224/73253 ,  Y10T29/49144

Abstract: An electronic package (10) having enhanced heat dissipation is provided exhibiting dual conductive heat paths (40, 42) in opposing directions. The package (10) includes a substrate (16) having electrical conductors thereon and a flip chip (12) mounted to the substrate (16). The flip chip (12) has a first surface, solder bumps (14) on the first surface, and a second surface oppositely disposed from the first surface. The flip chip (12) is mounted to the substrate (16) such that the solder bumps (14) are registered with the conductors on the substrate (16). The package (10) further includes a stamped metal heat sink (30) in heat transfer relationship with the second surface of the flip chip (12). The heat sink (30) includes a cavity (32) formed adjacent to the flip chip (12) containing a thermally conductive material (34).

Abstract translation: 提供具有增强的散热的电子封装（10），其在相反的方向上呈现出双重传导热路（40,42）。 封装（10）包括其上具有电导体的衬底（16）和安装到衬底（16）的倒装芯片（12）。 倒装芯片（12）具有第一表面，第一表面上的焊料凸块（14）和与第一表面相对设置的第二表面。 倒装芯片（12）安装到基板（16），使得焊料凸块（14）与基板（16）上的导体对准。 封装（10）还包括与倒装芯片（12）的第二表面传热关系的冲压金属散热器（30）。 散热器（30）包括与包含导热材料（34）的倒装芯片（12）相邻形成的空腔（32）。

公开(公告)号：EP1748688A3

公开(公告)日：2009-06-03

申请号：EP06076287.9

申请日：2006-06-23

Applicant: Delphi Technologies, Inc.

Inventor： Berlin, Carl W. ,  Chengalva, Suresh K. ,  Brandenburg, Scott D. ,  Myers, Bruce A.

IPC: H05K7/20

CPC classification number: H01L23/473 ,  H01L23/44 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/09701 ,  H01L2924/1305 ,  H01L2924/13055 ,  H05K7/20236 ,  H05K7/20909 ,  H01L2924/00014 ,  H01L2924/00

Abstract: An electronic package having circulated submersed cooling fluid and method are provided. The electronic package has a housing defining a sealed enclosure and electronic devices located in the housing. The electronic devices have thermal emitting electrical circuitry. A dielectric fluid, such as a liquid, is located in the housing in heat transfer relationship with the electronic devices. A fluid circulator, such as a piezo fan, is located in the housing in contact with the dielectric liquid for circulating the dielectric liquid to cool the electronic devices.

公开(公告)号：EP1558065A3

公开(公告)日：2007-11-14

申请号：EP05075085.0

申请日：2005-01-11

Applicant: Delphi Technologies, Inc.

Inventor： Chengalva, Mahesh K. ,  Chengalva, Suresh K. ,  Snyder, Rick B.

IPC: H05K1/02 ,  H05K3/46

CPC classification number: H05K1/112 ,  H01L2224/16225 ,  H05K1/0271 ,  H05K3/4644 ,  H05K3/4688 ,  H05K2201/0133 ,  H05K2201/10636 ,  H05K2201/10674 ,  H05K2201/10727 ,  Y02P70/611 ,  Y10T428/24273

Abstract: Surface mounting of components includes providing a substrate (10) that has a first surface and a second surface. A portion of the first surface is coupled to a conductive layer (20) that is patterned. A compliant layer (50) is introduced to the first surface of the substrate (10) and to the conductive layer (20). At least one aperture is formed in the compliant layer (50) which extends to the surface of the conductive layer (20). Conductive material is introduced into the aperture(s). Solder couples the surface mount component (90) to the compliant layer (50).

Abstract translation: 组件的表面安装包括提供具有第一表面和第二表面的基底（10）。 第一表面的一部分耦合到被图案化的导电层（20）。 柔性层（50）被引入衬底（10）的第一表面和导电层（20）。 在柔性层（50）中形成至少一个孔，其延伸到导电层（20）的表面。 将导电材料引入孔中。 焊接将表面安装部件（90）耦合到柔性层（50）。

公开(公告)号：EP1534052A3

公开(公告)日：2007-10-24

申请号：EP04078154.4

申请日：2004-11-18

Applicant: Delphi Technologies, Inc.

Inventor： Chengalva, Suresh K. ,  Ihms, David W. ,  Myers, Bruce A.

IPC: H05K1/02 ,  H01L23/00

CPC classification number: H05K1/0206 ,  H01L2224/16225 ,  H01L2224/73204 ,  H05K1/0271 ,  H05K3/0061 ,  H05K2201/068 ,  H05K2201/10204 ,  H05K2201/10545 ,  H05K2201/10674 ,  H05K2201/2009

Abstract: A circuit board assembly (10) comprising a laminate substrate (12) and a surface mount device (18) having a CTE less than that of the laminate substrate (12) and attached with at least one solder joint (20) to a first surface (14) of the laminate substrate (12). The assembly (10) further includes a localized stiffener (24,124,224) attached to a second surface (16) of the laminate substrate (12) so as to be directly opposite the circuit device (18). The localized stiffener (24,124,224) is formed of a material and is shaped so that, when attached to the laminate substrate (12), the stiffener (24,124,224) is capable of increasing the thermal cycle fatigue life of the one or more solder joints (20) that attach the device (18) to the substrate (12).

公开(公告)号：EP1667226A2

公开(公告)日：2006-06-07

申请号：EP05077632.7

申请日：2005-11-18

Applicant: Delphi Technologies, Inc.

Inventor： Fairchild, M. Ray ,  Zimmerman, David W. ,  Chengalva, Suresh K.

IPC: H01L23/36 ,  H05K7/20

CPC classification number: H05K1/021 ,  H01L23/13 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5389 ,  H01L24/48 ,  H01L25/16 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/4847 ,  H01L2224/73265 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19107 ,  H05K1/0306 ,  H05K1/183 ,  H05K3/0061 ,  H05K3/4611 ,  H05K3/4629 ,  H05K2201/09745 ,  H05K2201/1056 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A circuit board assembly (40,50) having a laminate construction of multiple layers (12), such as a LTCC ceramic substrate (10), with conductor lines (30) between adjacent pairs of layers (12). A heat sink (22) is bonded to a first surface (26) of the substrate (10), and a cavity (24) is defined by and between the heat sink (22) and the substrate (10) such that a base wall (28) of the cavity (24) is defined by one of the layers (12) with conductor lines (30) thereof being present on the base wall (28). A surface-mount circuit device (14) is received within the cavity (24), mounted to the base wall (28), and electrically connected to the conductor lines (30) on the base wall (28). The device (14) is received within the cavity (24) such that a surface of the device (14) contacts a surface region of the heat sink (22). The surface of the device (14) is bonded to the surface region of the heat sink (22) to provide a substantially direct thermal path from the device (14) to the heat sink (22).

Abstract translation: 电路板组件（40,50）具有多层（12）的叠层结构，例如LTCC陶瓷衬底（10），在相邻的层对（12）之间具有导线（30）。 散热器（22）被结合到基板（10）的第一表面（26）上，并且在散热器（22）和基板（10）之间由散热器（22）和基板（10）之间限定空腔（24），使得底壁 腔（24）中的一个（28）由其中一个层（12）限定，其中导体线（30）存在于基壁（28）上。 表面安装电路装置（14）被容纳在空腔（24）内，安装到基壁（28），并且电连接到基壁（28）上的导线（30）。 装置（14）被容纳在空腔（24）内，使得装置（14）的表面接触散热器（22）的表面区域。 装置（14）的表面结合到散热器（22）的表面区域，以提供从装置（14）到散热器（22）的基本上直接的热路径。