公开(公告)号：JP2004193605A

公开(公告)日：2004-07-08

申请号：JP2003405153

申请日：2003-12-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DALTON TIMOTHY J ,  DAS SANJIT K ,  ENGEL BRETT H ,  HERBST BRIAN W ,  HICHRI HABIB ,  KASTENMEIER BERND E ,  MALONE KELLY ,  MARINO JEFFREY R ,  MARTIN ARTHUR ,  MCGAHAY VINCENT J ,  MELVILLE IAN D ,  NARAYAN CHANDRASEKHAR ,  PETRARCA KEVIN S ,  VOLANT RICHARD P

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76808 ,  H01L21/76801 ,  H01L21/76831 ,  H01L23/5226 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/12044 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a structure and a method for reducing thermal mechanical stress in stack and via. SOLUTION: An interconnection structure for a semiconductor device comprises an organic low-k (low specific dielectric constant) dielectric layer formed on a lower metallization. The via to be formed here is in this low-k dielectric layer, and combines a lower metallization line formed on the lower metallization level and an upper metallization line formed on an upper metallization level. This via is surrounded by structure collar selected from material with CTE that can protect the via from shearing force generated after the thermal expansion of the low-k dielectric layer. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：CA2089791C

公开(公告)日：1998-11-24

申请号：CA2089791

申请日：1993-02-18

Applicant: IBM

Inventor： BRADY MICHAEL J ,  MARINO JEFFREY R ,  FARRELL CURTIS E ,  KANG SUNG K ,  PURUSHOTHAMAN SAMPATH ,  MIKALSEN DONALD J ,  MOSKOWITZ PAUL A ,  O'SULLIVAN EUGENE J ,  O'TOOLE TERRENCE R ,  RIELEY SHELDON C ,  WALKER GEORGE F

IPC: H01L21/60 ,  C23C18/50 ,  C25D3/54 ,  H01L21/288 ,  H01L21/603 ,  H01L21/768 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

Abstract: Silicon and germanium containing materials are used as a surface of conductors i n electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these s urfaces. These materials are used as a surface coating for lead frames for packaging inte grated circuit chips. These materials can be decal transferred onto conductor surfaces or elect rolessly or electrolytically disposed thereon.

公开(公告)号：BR9301497A

公开(公告)日：1993-10-26

申请号：BR9301497

申请日：1993-04-12

Applicant: IBM

Inventor： BRADY MICHAEL J ,  FARREL CURTIS E ,  KANG SUNG K ,  MARINO JEFFREY R ,  MIKALSEN DONALD J ,  MOSKOWITZ PAUL A ,  O'SULLIVAN EUGENE J ,  TOOLE TERRENCE R O ,  PURUSHOTHAMAN SAMPATH ,  RIELEY SHELDON C ,  WALKER GEORGE F

IPC: H01L21/60 ,  C23C18/50 ,  C25D3/54 ,  H01L21/288 ,  H01L21/603 ,  H01L21/768 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532 ,  H01L21/40

Abstract: Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

公开(公告)号：CA2089791A1

公开(公告)日：1993-10-25

申请号：CA2089791

申请日：1993-02-18

Applicant: IBM

Inventor： BRADY MICHAEL J ,  FARRELL CURTIS E ,  KANG SUNG K ,  MARINO JEFFREY R ,  MIKALSEN DONALD J ,  MOSKOWITZ PAUL A ,  O'SULLIVAN EUGENE J ,  O'TOOLE TERRENCE R ,  PURUSHOTHAMAN SAMPATH ,  RIELEY SHELDON C ,  WALKER GEORGE F

IPC: H01L21/60 ,  C23C18/50 ,  C25D3/54 ,  H01L21/288 ,  H01L21/603 ,  H01L21/768 ,  H01L23/495 ,  H01L23/498 ,  H01L23/532

Abstract: Silicon and germanium containing materials are used at surface of conductors in electronic devices. Solder can be fluxlessly bonded and wires can be wire bonded to these surfaces. These material are used as a surface coating for lead frames for packaging integrated circuit chips. These materials can be decal transferred onto conductor surfaces or electrolessly or electrolytically disposed thereon.

公开(公告)号：CA2514454A1

公开(公告)日：2004-08-19

申请号：CA2514454

申请日：2004-01-23

Applicant: IBM

Inventor： SIMON ANDREW H ,  GEFFKEN ROBERT M ,  MARINO JEFFREY R ,  COONEY EDWARD C III ,  STAMPER ANTHONY K

IPC: H01L21/768

Abstract: A semiconductor device which includes an improved liner structure formed in a via having extended sidewall portions and a bottom penetrating a metal line. The liner structure includes two liner layers, the first being on the via sidewalls, but not the bottom, and the second being on the first layer and the extended sidewall portions and bottom of the via. A method of making the liner structure, in which the first layer is deposited prior to an etching or cleaning step, which extends the via into the metal line, is also disclosed.