公开(公告)号：EP4220734A1

公开(公告)日：2023-08-02

申请号：EP23152421.6

申请日：2023-01-19

Applicant: STMicroelectronics S.r.l.

Inventor： IUCOLANO, Ferdinando ,  LO NIGRO, Raffaella ,  SCHILIRO', Emanuela ,  ROCCAFORTE, Fabrizio

IPC: H01L29/51 ,  H01L29/16 ,  H01L21/04 ,  H01L21/28 ,  H01L29/20 ,  H01L29/778 ,  H01L29/78

Abstract: A wide band gap transistor includes a semiconductor structure (2), having at least one wide band gap semiconductor layer (14, 16) of gallium nitride (GaN) or silicon carbide (SiC), an insulating gate structure (8) and a gate electrode (7), separated from the semiconductor structure (2) by the insulating gate structure (8). The insulating gate structure (8) contains a mixture of aluminum, hafnium and oxygen and is completely amorphous.

公开(公告)号：EP4020595A1

公开(公告)日：2022-06-29

申请号：EP21217608.5

申请日：2021-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  ZANETTI, Edoardo ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/12 ,  H01L29/08

Abstract: A MOSFET transistor device has: a functional layer (24) of silicon carbide, having a first conductivity type; gate structures (30) formed on a top surface (24a) of the functional layer and each comprising a dielectric region (31) and an electrode region (32); body wells (26) having a second conductivity type, formed within the functional layer, separated from one another by surface-separation regions (29); source regions (27) having the first conductivity type, formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions (40) are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

公开(公告)号：EP3742496A1

公开(公告)日：2020-11-25

申请号：EP20176149.1

申请日：2020-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/872 ,  H01L21/336 ,  H01L29/12

Abstract: An electronic device comprising: a semiconductor body (48; 68) of silicon carbide, SiC, having a first (48a; 68a) and a second face (48b; 68b), opposite to one another along a first direction (Z), which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal (S; 74), which extends at the first face of the semiconductor body; a second conduction terminal (D; 72), which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer (52; 80), of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：EP4231360A1

公开(公告)日：2023-08-23

申请号：EP23156230.7

申请日：2023-02-13

Applicant: STMicroelectronics S.r.l.

Inventor： IUCOLANO, Ferdinando ,  SEVERINO, Andrea ,  GRECO, Giuseppe ,  ROCCAFORTE, Fabrizio

IPC: H01L29/778 ,  H01L21/338 ,  H01L29/417 ,  H01L29/20

Abstract: For the manufacturing of a HEMT device (50), from a wafer (2) of silicon carbide having a surface (2A), an epitaxial layer (4) of silicon carbide is formed on the surface (2A) of the wafer (2), a semiconductive heterostructure (5) is formed on the epitaxial layer, and the wafer of silicon carbide is removed.

公开(公告)号：EP4220687A1

公开(公告)日：2023-08-02

申请号：EP23152626.0

申请日：2023-01-20

Applicant: STMicroelectronics S.r.l.

Inventor： IUCOLANO, Ferdinando ,  GRECO, Giuseppe ,  BADALA', Paolo ,  ROCCAFORTE, Fabrizio ,  SPERA, Monia

IPC: H01L21/285 ,  H01L29/45 ,  H01L21/335 ,  H01L29/778 ,  H01L21/027 ,  H01L29/20 ,  H01L29/417

Abstract: For manufacturing a HEMT device (1), a conductive region (15, 16) is formed on a work body (50) having a semiconductive heterostructure (8). To obtain the conductive region, a first reaction region (66) having carbon is formed on the heterostructure; and a metal stack (70) is formed having a second reaction region (70A) in contact with the first reaction region. The work body is annealed, so that the first reaction region (66) reacts with the second reaction region (70A), thus forming an interface portion (25) of the conductive region. The interface portion is of a compound having carbon and is in ohmic contact with the semiconductive heterostructure.

公开(公告)号：EP4333073A1

公开(公告)日：2024-03-06

申请号：EP23182331.1

申请日：2023-06-29

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  ZANETTI, Edoardo ,  SAGGIO, Mario Giuseppe

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/872 ,  H01L21/336 ,  H01L29/12

Abstract: Electronic device (20; 60) comprising: a semiconductor body (48; 68), in particular of Silicon Carbide, SiC, having a first (48a; 68a) and a second face (48b; 68b), opposite to each other along a first direction (Z); and an electrical terminal (G; 82, 74) at the first face (48b; 68b), insulated from the semiconductor body (48; 68) by an electrical insulation region (52; 80). The electrical insulation region is a multilayer comprising: a first insulating layer (102), of a Silicon Oxide, in contact with the semiconductor body; a second insulating layer (104) on the first insulating layer (102), of a Hafnium Oxide; and a third insulating layer (106) on the second insulating layer (104), of an Aluminum Oxide.

公开(公告)号：EP4246554A1

公开(公告)日：2023-09-20

申请号：EP23161718.4

申请日：2023-03-14

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA', Simone ,  ROCCAFORTE, Fabrizio ,  BELLOCCHI, Gabriele ,  VIVONA, Marilena

IPC: H01L21/20 ,  H01L29/04 ,  H01L29/872 ,  H01L21/02 ,  H01L29/06 ,  H01L29/16

Abstract: Method for manufacturing an electronic device (50; 80), comprising the steps of: forming, at a front side (2a) of a solid body (3, 2) of 4H-SiC having a first electrical conductivity (N), at least one implanted region (9') having a second electrical conductivity (P) opposite to the first electrical conductivity (N); forming, on the front side (2a), a 3C-SiC layer (52); and forming, in the 3C-SiC layer (52), an ohmic contact region (54; 84) which extends through the entire thickness of the 3C-SiC layer (52), up to reaching the implanted region (9'). A Silicon layer (56) may be present on the 3C-SiC layer; in this case, the ohmic contact also extends through the Silicon layer.

公开(公告)号：EP4220735A1

公开(公告)日：2023-08-02

申请号：EP23153642.6

申请日：2023-01-27

Applicant: STMicroelectronics S.r.l.

Inventor： IUCOLANO, Ferdinando ,  GIANNAZZO, Filippo ,  GRECO, Giuseppe ,  ROCCAFORTE, Fabrizio

IPC: H01L29/778 ,  H01L21/337 ,  H01L21/265 ,  H01L29/10 ,  H01L29/267 ,  H01L29/423 ,  H01L29/08 ,  H01L29/20

Abstract: High-electron-mobility transistor, HEMT, device (20) in enhancement-mode, comprising: a semiconductor body (35) having a top surface (27b) and including a heterostructure (25, 27) configured to generate a two-dimensional electron gas, 2DEG, (31); and
- a gate structure (32) which extends on the top surface (27b) of the semiconductor body (35), is biasable to electrically control the 2DEG (31) and comprises a functional layer (34) and a gate contact (33) in direct physical and electrical contact with each other. The gate contact (33) is of conductive material and the functional layer (34) is of two-dimensional semiconductor material and comprises a first doped portion (40') with P-type electrical conductivity, which extends on the top surface (27b) of the semiconductor body (35) and is interposed between the semiconductor body (35) and the gate contact (33) along a first axis (Z).

公开(公告)号：EP4152406A1

公开(公告)日：2023-03-22

申请号：EP22193143.9

申请日：2022-08-31

Applicant: STMicroelectronics S.r.l.

Inventor： GIANNAZZO, Filippo ,  GRECO, Giuseppe ,  ROCCAFORTE, Fabrizio ,  RASCUNÀ, Simone

IPC: H01L29/06 ,  H01L29/267 ,  H01L29/66 ,  H01L29/872

Abstract: Merged-PiN-Schottky, MPS, device (50) comprising: a solid body (52, 53) having a first electrical conductivity (N); an implanted region (59) extending into the solid body (52, 53) facing a front side (52a) of the solid body (52, 53), having a second electrical conductivity (P) opposite to the first electrical conductivity (N); and a semiconductor layer (61) extending on the front side (52a), of a material which is a transition metal dichalcogenide, TMD. A first region (61') of the semiconductor layer (61) has the second electrical conductivity (P) and extends in electrical contact with the implanted region (59), and a second region (61") of the semiconductor layer (61) has the first electrical conductivity (N) and extends adjacent to the first region (61') and in electrical contact with a respective surface portion of the front side (52a) having the first electrical conductivity (N).

公开(公告)号：EP3413353A1

公开(公告)日：2018-12-12

申请号：EP18176876.3

申请日：2018-06-08

Applicant: STMicroelectronics S.r.l.

Inventor： IUCOLANO, Ferdinando ,  GRECO, Giuseppe ,  ROCCAFORTE, Fabrizio

IPC: H01L29/778

CPC classification number: H01L29/7786 ,  H01L23/291 ,  H01L29/1066 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/207 ,  H01L29/41766 ,  H01L29/4236 ,  H01L29/66462 ,  H01L29/7378

Abstract: Normally-off HEMT transistor (1; 21; 31) comprising a heterostructure (3) including a channel layer (4) and a barrier layer (6) on the channel layer (4); a 2DEG layer in the heterostructure (3); an insulation layer (7) in contact with a first region of the barrier layer (6); and a gate electrode (8) through the whole thickness of the insulation layer (7), terminating in contact with a second region (6') of the barrier layer (6). The barrier layer (6) and the insulation layer (7) have a mismatch of the lattice constant ("lattice mismatch"), which generates a mechanical stress solely in the first region of the barrier layer (6), giving rise to a first concentration of electrons (n s ) in a first portion of the two-dimensional conduction channel which is under the first region of the barrier layer (6) which is greater than a second concentration of electrons (n s ) in a second portion of the two-dimensional conduction channel which is under the second region (6') of the barrier layer (6) .