公开(公告)号：US10993319B1

公开(公告)日：2021-04-27

申请号：US16939243

申请日：2020-07-27

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yu-Chen Ma ,  Hsin-Hao Huang ,  Wen-Fu Chou ,  Gwo-Shyan Sheu

IPC: H05K1/02 ,  H05K1/18 ,  H05K3/28

Abstract: A chip package includes a circuit board, a chip and an underfill. A solder resist layer formed on the circuit board is modified in edge profile so as to reduce required amount of the underfill. The fewer underfill is still enough to be filled between the circuit board and the chip, and still can cover circuit lines that are not covered by the solder resist layer to protect the circuit lines from oxidation.

公开(公告)号：US20200231406A1

公开(公告)日：2020-07-23

申请号：US16354282

申请日：2019-03-15

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chung-Yi Chang

IPC: B65H75/18

Abstract: A restriction device for preventing deformation of restriction plate of reel is disclosed. The restriction device includes a first circular restrictor, a second circular restrictor, a block member and a first push member. A clamping space exists between the first and second circular restrictors mounted on a shaft and is configured to accommodate a reel mounted on the shaft. The second circular restrictor is able to be moved on the shaft in an axial direction, the block member is fixed on the shaft and the first push member is placed between the block member and the second circular restrictor. The first push member is configured to apply a force to push the second circular restrictor toward the first circular restrictor to press a first restriction plate of the reel such that the deformation of the first restriction plate is prevented.

公开(公告)号：US20180211860A1

公开(公告)日：2018-07-26

申请号：US15456652

申请日：2017-03-13

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chien-Ming Kuo ,  Hung-Ching Chang

IPC: H01L21/677 ,  H01L21/673

CPC classification number: H01L21/67766 ,  H01L21/00 ,  H01L21/6732 ,  H01L21/67379 ,  H01L21/67383 ,  H01L21/67386 ,  H01L21/67769 ,  H01L21/67778

Abstract: A wafer cassette for storing wafers comprises a case and a plurality of carriers for carrying the wafers. Each of the carriers is pivotally and movably mounted to a pivot of the case, and can selectively accommodate in or depart from an accommodation space of the case for benefit of the wafer loading or unloading.

公开(公告)号：US09961759B2

公开(公告)日：2018-05-01

申请号：US15279657

申请日：2016-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Fei-Jain Wu ,  Chia-Jung Tu

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/03 ,  H05K1/18

CPC classification number: H05K1/0209 ,  H05K1/0203 ,  H05K1/028 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/189 ,  H05K2201/0154 ,  H05K2201/066 ,  H05K2201/068

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

公开(公告)号：US20170019984A1

公开(公告)日：2017-01-19

申请号：US15279657

申请日：2016-09-29

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Fei-Jain Wu ,  Chia-Jung Tu

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0209 ,  H05K1/0203 ,  H05K1/028 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/189 ,  H05K2201/0154 ,  H05K2201/066 ,  H05K2201/068

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract translation: 柔性基板包括电路板，柔性散热结构和粘合剂。 电路基板具有形成在基板顶面的基板和电路层，柔性散热结构具有柔性支撑板和形成在柔性支撑板的表面上的柔性散热金属层。 柔性散热结构的柔性散热金属层通过粘合剂与基板的底面连接。 电路层和柔性散热金属层由相同的材料制成。

公开(公告)号：US09508676B1

公开(公告)日：2016-11-29

申请号：US14848439

申请日：2015-09-09

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Cheng-Hung Shih ,  Yung-Wei Hsieh ,  Shu-Chen Lin ,  Fu-Yen Ho ,  Yen-Ting Chen

IPC: H01L23/00

CPC classification number: H01L24/83 ,  H01L21/50 ,  H01L23/10 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/13005 ,  H01L2224/13014 ,  H01L2224/14179 ,  H01L2224/16245 ,  H01L2224/83815 ,  H01L2924/014 ,  H01L2924/1461 ,  H01L2924/16152 ,  H01L2924/16195 ,  H01L2924/165

Abstract: A semiconductor package structure having hollow chamber includes a bottom substrate having a bottom baseboard and a bottom metal layer formed on a disposing area of the bottom baseboard, a connection layer formed on the bottom metal layer, and a top substrate. The bottom metal layer has at least one corner having a first and a second outer lateral surface, and an outer connection surface. A first extension line is formed from a first extreme point of the first outer lateral surface, and a second extension line is formed from a second extreme point of the second outer lateral surface. A first exposing area of the bottom baseboard is formed by connecting the first and second extreme points and a cross point of the first and second extreme points. The top substrate connects to the connection layer to form a hollow chamber between the top and bottom substrates.

Abstract translation: 具有中空室的半导体封装结构包括：底部基板，具有形成在底部基板的设置区域上的底部基板和底部金属层，形成在底部金属层上的连接层和顶部基板。 底部金属层具有至少一个具有第一和第二外侧表面的角部和外部连接表面。 第一延伸线由第一外侧表面的第一极点形成，第二延伸线由第二外侧表面的第二极限点形成。 通过连接第一极点和第二极值点以及第一和第二极值点的交叉点来形成底部基板的第一暴露区域。 顶部衬底连接到连接层，以在顶部和底部衬底之间形成中空室。

公开(公告)号：US20160234927A1

公开(公告)日：2016-08-11

申请号：US14642945

申请日：2015-03-10

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chin-Tang Hsieh ,  Fei-Jain Wu ,  Chia-Jung Tu

IPC: H05K1/02 ,  H05K1/03

CPC classification number: H05K1/0209 ,  H05K1/0203 ,  H05K1/028 ,  H05K1/0346 ,  H05K1/0393 ,  H05K1/189 ,  H05K2201/0154 ,  H05K2201/066 ,  H05K2201/068

Abstract: A flexible substrate includes a circuit board, a flexible heat-dissipating structure and an adhesive. The circuit board has a substrate and a circuit layer formed on a top surface of the substrate, and the flexible heat-dissipating structure has a flexible supporting plate and a flexible heat-dissipating metal layer formed on a surface of the flexible supporting plate. The flexible heat-dissipating metal layer of the flexible heat-dissipating structure is connected with a bottom surface of the substrate by the adhesive. The circuit layer and the flexible heat-dissipating metal layer are made of same material.

Abstract translation: 柔性基板包括电路板，柔性散热结构和粘合剂。 电路基板具有形成在基板顶面的基板和电路层，柔性散热结构具有柔性支撑板和形成在柔性支撑板的表面上的柔性散热金属层。 柔性散热结构的柔性散热金属层通过粘合剂与基板的底面连接。 电路层和柔性散热金属层由相同的材料制成。

公开(公告)号：US09247635B2

公开(公告)日：2016-01-26

申请号：US14317254

申请日：2014-06-27

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yi-Wen Chen ,  Yin-Chen Lin ,  Ming-Hsiao Ke ,  Yu-Chen Ma

IPC: H05K1/00 ,  H05K1/02

CPC classification number: H05K1/0269 ,  H05K1/0274 ,  H05K1/028 ,  H05K1/0298 ,  H05K2201/09781 ,  H05K2201/0989 ,  H05K2201/09936

Abstract: A flexible substrate includes a base layer, a metallic layer, a solder mask layer and an identifying code, the metallic layer is disposed at a first surface of the base layer, the metallic layer comprises a plurality of traces and at least one bottom block used for defining marked position, wherein the traces and the at least one bottom block are covered with the solder mask layer, wherein above the perpendicular direction of the at least one bottom block of the metallic layer, a pre-marked area is defined on an exposing surface of the solder mask layer and by an outlined edge of the at least one bottom block, and the identifying code is formed within the pre-marked area of the solder mask layer.

Abstract translation: 柔性基板包括基底层，金属层，焊接掩模层和识别代码，金属层设置在基底层的第一表面，金属层包括多个迹线和至少一个使用的底部块 用于限定标记位置，其中所述迹线和所述至少一个底部块被所述焊接掩模层覆盖，其中在所述金属层的所述至少一个底部块的垂直方向上方，预先标记的区域被限定在曝光 焊料掩模层的表面和至少一个底部块的轮廓边缘，并且识别代码形成在焊料掩模层的预先标记的区域内。

公开(公告)号：US20160020166A1

公开(公告)日：2016-01-21

申请号：US14515719

申请日：2014-10-16

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Yung-Wei Hsieh ,  Cheng-Hung Shih ,  Kai-Yi Wang ,  Heh-Chang Huang ,  Po-Hao Chen

IPC: H01L23/50

CPC classification number: H01L23/49838 ,  H01L21/4846

Abstract: A trace structure of fine-pitch pattern includes a connection portion, a first conductive wire portion and a second conductive wire portion, the first conductive wire portion comprises a first section and a second section connected to the first section, the first section connects to the connection portion, the second conductive wire portion comprises a third section and a fourth section connected to the third section, the third section connects to the connection portion, wherein an etching space closed on three sides is formed by the connection portion, the third section and the first section, a first spacing is defined between the third section and the first section, a second spacing is defined between the fourth section and the second section, wherein the first spacing is larger than the second spacing so as to make an metal layer within the etching space completely removed to avoid metal layer residues.

Abstract translation: 细间距图案的迹线结构包括连接部分，第一导线部分和第二导线部分，第一导线部分包括连接到第一部分的第一部分和第二部分，第一部分连接到 连接部分，第二导线部分包括连接到第三部分的第三部分和第四部分，第三部分连接到连接部分，其中通过连接部分，第三部分和第三部分形成三面封闭的蚀刻空间， 所述第一部分在所述第三部分和所述第一部分之间限定第一间隔，在所述第四部分和所述第二部分之间限定第二间隔，其中所述第一间隔大于所述第二间隔，以使所述第一部分内的金属层在 蚀刻空间完全去除以避免金属层残留。

公开(公告)号：US09059260B2

公开(公告)日：2015-06-16

申请号：US14164628

申请日：2014-01-27

Applicant: CHIPBOND TECHNOLOGY CORPORATION

Inventor： Chih-Ming Kuo ,  Lung-Hua Ho ,  Shih-Chieh Chang ,  Chia-Yeh Huang ,  Chin-Tang Hsieh

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L21/76885 ,  H01L21/4853 ,  H01L23/48 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/13006 ,  H01L2224/13016 ,  H01L2224/13023 ,  H01L2224/13076 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: A semiconductor manufacturing method includes providing a carrier; forming a first photoresist layer; forming plural core portions; removing the first photoresist layer; forming a second photoresist layer; forming a plurality of connection portions, each of the plurality of connection portions includes a first connection layer and a second connection layer and connects to each of the core portions to form a hybrid bump, wherein each of the first connection layers comprises a base portion, a projecting portion and an accommodating space, each base portion comprises an upper surface, each projecting portion is protruded to the upper surface and located on top of each core portion, each accommodating space is located outside each projecting portion, the second connection layers cover the projecting portions and the upper surfaces, and the accommodating spaces are filled by the second connection layers; removing the second photoresist layer to reveal the hybrid bumps.

Abstract translation: 半导体制造方法包括提供载体; 形成第一光致抗蚀剂层; 形成多个芯部; 去除第一光致抗蚀剂层; 形成第二光致抗蚀剂层; 形成多个连接部分，所述多个连接部分中的每一个包括第一连接层和第二连接层，并且连接到每个所述芯部分以形成混合凸块，其中每个所述第一连接层包括基部， 突出部分和容纳空间，每个基部包括上表面，每个突出部分突出到上表面并且位于每个芯部的顶部，每个容纳空间位于每个突出部分的外侧，第二连接层覆盖 突出部分和上表面，并且容纳空间被第二连接层填充; 去除第二光致抗蚀剂层以露出混合凸块。