公开(公告)号：US20080005901A1

公开(公告)日：2008-01-10

申请号：US11901162

申请日：2007-09-14

Applicant: My Jang

Inventor： My Jang

IPC: H05K3/34 ,  H05K1/16 ,  H05K3/30

CPC classification number: H05K3/3442 ,  H05K3/303 ,  H05K2201/0166 ,  H05K2201/09472 ,  H05K2201/10393 ,  H05K2201/10636 ,  H05K2201/2018 ,  H05K2203/0169 ,  H05K2203/0594 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Methods and apparatus to couple a device, such as, for example, a surface mount device, with a substrate, such as, for example, a printed circuit, are disclosed. An apparatus, according to one aspect, may include a substrate, a plurality of terminals coupled with the substrate, a conductive bonding material coupled with the plurality of terminals, an electronic device coupled with the conductive bonding material, and a holder that is coupled with the substrate to hold the electronic device. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed therebetween, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract translation: 公开了将诸如例如表面贴装装置的装置与衬底（例如印刷电路）耦合的方法和装置。 根据一个方面的装置可以包括衬底，与衬底耦合的多个端子，与多个端子耦合的导电接合材料，与导电接合材料耦合的电子器件，以及与 保持电子设备的基板。 根据一个方面的一种方法可以包括将保持器与衬底连接，使得衬底的端子包括在保持器的开口中，将电子器件安装在端子之间，其间设置有导电接合材料，加热导电接合 材料到其熔点，并冷却导电接合材料。

公开(公告)号：US20070163111A1

公开(公告)日：2007-07-19

申请号：US11728406

申请日：2007-03-26

Applicant: Yutaka Kaneda

Inventor： Yutaka Kaneda

IPC: H05K3/20

CPC classification number: H05K3/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/0166 ,  H05K2201/0367 ,  H05K2203/056 ,  H05K2203/0733 ,  H05K2203/1545 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: In one embodiment, the present invention provides a process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.

Abstract translation: 在一个实施例中，本发明提供一种制造多层挠性布线板的方法，其允许各层布线板精确定位并容易堆叠。 制备用于曝光的掩模，其中与垂直于基板的传送方向P的方向布置与多层柔性布线板的布线板的各层相对应的多个图案孔。 该曝光用掩模用于形成与同一片状基板上的多层柔性布线基板的各层布线基板对应的多个布线图案。

公开(公告)号：US20070111561A1

公开(公告)日：2007-05-17

申请号：US11565715

申请日：2006-12-01

Applicant: Alan Wang ,  Kevin Olson ,  Thomas DiStefano

Inventor： Alan Wang ,  Kevin Olson ,  Thomas DiStefano

IPC: H01R12/00

CPC classification number: H05K1/0231 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/44 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/0919 ,  H05K2201/09309 ,  H05K2201/09554 ,  H05K2201/10446 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49156

Abstract: Provided is a method of forming a circuit board including (a) providing a first conductive sheet; (b) selectively removing one or more portions of the first conductive sheet to form a first panel having a first circuit board that is coupled to a disposable part of the first panel by at least one tab that extends from an edge of the first circuit board to an edge of the disposable part of the first panel; (c) applying an insulating coating to the first circuit board so that at least each edge of the first circuit board is covered thereby; and (d) separating the first circuit board from the disposable part in a manner whereupon at least part of the tab remains attached to the first circuit board and includes an exposed edge of the conductive sheet of the first circuit board. Circuit boards formed by the method are also provided.

Abstract translation: 提供一种形成电路板的方法，包括：（a）提供第一导电片; （b）选择性地去除所述第一导电片的一个或多个部分以形成具有第一电路板的第一面板，所述第一电路板通过从所述第一电路板的边缘延伸的至少一个接片连接到所述第一面板的一次性部分 到所述第一面板的一次性部分的边缘; （c）向第一电路板施加绝缘涂层，使得第一电路板的至少每个边缘被覆盖; 和（d）以一种方式将第一电路板与一次性部分分离，由此至少部分突片保持附接到第一电路板并且包括第一电路板的导电片的暴露边缘。 还提供了通过该方法形成的电路板。

公开(公告)号：US20060286696A1

公开(公告)日：2006-12-21

申请号：US11157531

申请日：2005-06-21

Applicant: Joel Peiffer ,  Nelson O'Bryan

Inventor： Joel Peiffer ,  Nelson O'Bryan

IPC: H01L21/00 ,  H01L33/00

CPC classification number: H05K1/162 ,  H05K1/095 ,  H05K1/16 ,  H05K1/167 ,  H05K3/429 ,  H05K2201/0166 ,  H05K2201/0209 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A passive electrical article includes a first electrically conductive substrate having a major surface and a second electrically conductive substrate having a major surface. The major surface of the second substrate faces the major surface of the first substrate. An electrically resistive layer is on at least one of the major surface of the first substrate and the major surface of the second substrate. An electrically insulative layer is between the first and second substrates and in contact with the electrically resistive layer. The insulative layer is a polymer having a thickness ranging from about 1 μm to about 20 μm. The insulative layer has a substantially constant thickness.

Abstract translation: 无源电器件包括具有主表面的第一导电衬底和具有主表面的第二导电衬底。 第二基板的主表面面向第一基板的主表面。 电阻层位于第一基板的主表面和第二基板的主表面中的至少一个上。 电绝缘层位于第一和第二基板之间并与电阻层接触。 绝缘层是厚度范围为约1μm至约20μm的聚合物。 绝缘层具有基本恒定的厚度。

公开(公告)号：US07144817B2

公开(公告)日：2006-12-05

申请号：US09905052

申请日：2001-07-12

Applicant: Hiroshi Samukawa

Inventor： Hiroshi Samukawa

IPC: H01L21/302 ,  C09K13/00

CPC classification number: C08J7/12 ,  C08J2379/08 ,  G03F7/40 ,  G03F7/405 ,  H05K3/002 ,  H05K3/28 ,  H05K3/4614 ,  H05K2201/0154 ,  H05K2201/0166 ,  H05K2201/0195 ,  H05K2203/0783 ,  H05K2203/0793

Abstract: The disclosure relates to methods and solutions for precisely and rapidly etching a polyimide resin layer. Etching solutions of the present invention include 3–65% by weight of a diol containing 3 to 6 carbon atoms or a triol containing 4 to 6 carbon atoms, 10–55 % by weight of an alkali compound and water in an amount of 0.75–3.0 times the amount of the alkali compound, and can be used at 65° C. or more to rapidly etch a polyimide resin layer having an imidation degree of 50–98 % without unfavorably affecting the working atmosphere. Even if the resin layer is completely imidated after etching, the etching pattern of the resulting resin layer is not deformed with a decreased contamination by impurity ions as compared with those obtained using conventional etching solutions.

公开(公告)号：US20060213685A1

公开(公告)日：2006-09-28

申请号：US11442016

申请日：2006-05-26

Applicant: Alan Wang ,  Kevin Olson

Inventor： Alan Wang ,  Kevin Olson

IPC: H05K1/11

CPC classification number: H05K3/445 ,  H01L2224/16225 ,  H05K1/056 ,  H05K3/002 ,  H05K3/0052 ,  H05K3/403 ,  H05K3/426 ,  H05K3/44 ,  H05K3/4614 ,  H05K3/4641 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2201/0397 ,  H05K2201/0909 ,  H05K2201/09154 ,  H05K2201/09181 ,  H05K2201/0919 ,  H05K2201/09554 ,  H05K2201/09645 ,  H05K2201/09827 ,  H05K2203/1105 ,  H05K2203/135 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A circuit board includes an electrically conductive sheet having an insulative coating surrounding the conductive sheet, with a surface of the insulative coating around an edge of the conductive sheet having an arcuate or rounded shape. At least one electrical conductor is conformally deposited on at least the rounded insulative coating around the edge of the conductive sheet and defined via photolithographic and metallization techniques. Each electrical conductor on the insulative coating thereon around the edge of the conductive sheet conforms to the arcuate or rounded shape of the insulative coating and, therefore, has an arcuate or rounded shape.

Abstract translation: 电路板包括具有围绕导电片的绝缘涂层的导电片，绝缘涂层的表面围绕导电片的边缘具有弓形或圆形形状。 至少一个电导体被共形沉积在导电片的边缘周围的至少圆形绝缘涂层上，并通过光刻和金属化技术限定。 导电片边缘周围的绝缘涂层上的每个电导体符合绝缘涂层的弧形或圆形形状，因此具有弓形或圆形形状。

公开(公告)号：US20060067065A1

公开(公告)日：2006-03-30

申请号：US10954463

申请日：2004-09-30

Applicant: Jang My

Inventor： Jang My

IPC: H05K7/06

CPC classification number: H05K3/3442 ,  H05K3/303 ,  H05K2201/0166 ,  H05K2201/09472 ,  H05K2201/10393 ,  H05K2201/10636 ,  H05K2201/2018 ,  H05K2203/0169 ,  H05K2203/0594 ,  H05K2203/0769 ,  Y02P70/611 ,  Y02P70/613 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49146 ,  Y10T29/49147 ,  Y10T29/49149 ,  Y10T29/49169 ,  Y10T29/49171

Abstract: Methods and apparatus to couple a device, such as, for example, a surface mount device, with a substrate, such as, for example, a printed circuit, are disclosed. An apparatus, according to one aspect, may include a substrate, a plurality of terminals coupled with the substrate, a conductive bonding material coupled with the plurality of terminals, an electronic device coupled with the conductive bonding material, and a holder that is coupled with the substrate to hold the electronic device. A method, according to one aspect, may include coupling a holder with a substrate such that terminals of the substrate are included in an opening of the holder, mounting an electronic device over the terminals with a conductive bonding material disposed therebetween, heating the conductive bonding material to its melting point, and cooling the conductive bonding material.

Abstract translation: 公开了将诸如例如表面贴装装置的装置与衬底（例如印刷电路）耦合的方法和装置。 根据一个方面的装置可以包括衬底，与衬底耦合的多个端子，与多个端子耦合的导电接合材料，与导电接合材料耦合的电子器件，以及与 保持电子设备的基板。 根据一个方面的一种方法可以包括将保持器与衬底连接，使得衬底的端子包括在保持器的开口中，将电子器件安装在端子之间，其间设置有导电接合材料，加热导电接合 材料到其熔点，并冷却导电接合材料。

公开(公告)号：US20060022310A1

公开(公告)日：2006-02-02

申请号：US10900386

申请日：2004-07-28

Applicant: Frank Egitto ,  John Lauffer ,  How Lin ,  Voya Markovich ,  David Thomas

Inventor： Frank Egitto ,  John Lauffer ,  How Lin ,  Voya Markovich ,  David Thomas

IPC: H01L23/58

CPC classification number: G11C5/06 ,  B82Y10/00 ,  G02B6/43 ,  H01L23/48 ,  H01L2224/0554 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/16 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4611 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: An electrical assembly which includes a circuitized substrate comprised of an organic dielectric material having a first electrically conductive pattern thereon. At least part of the dielectric layer and pattern form the first, base portion of an organic memory device, the remaining portion being a second, polymer layer formed over the part of the pattern and a second conductive circuit formed on the polymer layer. A second dielectric layer if formed over the second conductive circuit and first circuit pattern to enclose the organic memory device. The device is electrically coupled to a first electrical component through the second dielectric layer and this first electrical component is electrically coupled to a second electrical component. A method of making the electrical assembly is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract translation: 一种电气组件，其包括由其上具有第一导电图案的有机电介质材料构成的电路化衬底。 电介质层和图案的至少一部分形成有机存储器件的第一基底部分，其余部分是形成在图案部分上的第二聚合物层和形成在聚合物层上的第二导电电路。 如果形成在第二导电电路上的第二电介质层和第一电路图案以包围有机存储器件。 该器件通过第二介电层电耦合到第一电气部件，并且该第一电气部件电耦合到第二电气部件。 还提供了制造电气组件的方法，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

公开(公告)号：US20060022303A1

公开(公告)日：2006-02-02

申请号：US10900385

申请日：2004-07-28

Applicant: Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

Inventor： Subahu Desai ,  How Lin ,  John Lauffer ,  Voya Markovich ,  David Thomas

IPC: H01L29/00 ,  H01L21/00

CPC classification number: G11C11/22 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/3011 ,  H05K1/16 ,  H05K2201/0166 ,  H05K2201/0179 ,  H05K2201/09763 ,  H05K2201/10159 ,  H01L2224/0401

Abstract: A circuitized substrate comprised of at least one dielectric material having an electrically conductive pattern thereon. At least part of the pattern is used as the first layer of an organic memory device which further includes at least a second dielectric layer over the pattern and a second pattern aligned with respect to the lower part for achieving several points of contact to thus form the device. The substrate is preferably combined with other dielectric-circuit layered assemblies to form a multilayered substrate on which can be positioned discrete electronic components (e.g., a logic chip) coupled to the internal memory device to work in combination therewith. An electrical assembly capable of using the substrate is also provided, as is an information handling system adapted for using one or more such electrical assemblies as part thereof.

Abstract translation: 一种电路化衬底，由至少一层具有导电图案的电介质材料构成。 图案的至少一部分被用作有机存储器件的第一层，该有机存储器件还包括在图案上方的至少第二介电层和相对于下部对准的第二图案，用于实现几个接触点，从而形成 设备。 衬底优选地与其它介电电路分层组件组合以形成多层衬底，在多层衬底上，可以将耦合到内部存储器件的分立电子部件（例如，逻辑芯片）放置在其上以与之组合工作。 还提供了能够使用基板的电气组件，以及适于使用一个或多个这样的电气组件作为其一部分的信息处理系统。

公开(公告)号：US20050253235A1

公开(公告)日：2005-11-17

申请号：US11116046

申请日：2005-04-27

Applicant: Kazumi Hara

Inventor： Kazumi Hara

IPC: H01L23/29 ,  H01L23/00 ,  H01L23/02 ,  H01L23/31 ,  H01L29/06 ,  H05K1/02

CPC classification number: H01L23/562 ,  H01L23/3171 ,  H01L29/0657 ,  H01L2924/0002 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/0166 ,  H05K2201/0352 ,  H05K2201/068 ,  H05K2201/09136 ,  H05K2201/09736 ,  H05K2201/09909 ,  H05K2201/10674 ,  H01L2924/00

Abstract: A semiconductor chip is provided that is highly packageable and particularly well suited for mounting on a circuit board having a curved surface. The semiconductor chip comprises a warpage control film that controls the warpage of a substrate.

Abstract translation: 提供了一种高度可封装的半导体芯片，特别适用于安装在具有曲面的电路板上。 半导体芯片包括控制基板翘曲的翘曲控制膜。