公开(公告)号：US06670701B2

公开(公告)日：2003-12-30

申请号：US10000031

申请日：2001-12-04

Applicant: Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

Inventor： Tetsuya Matsuura ,  Yasushi Kasatani ,  Kazunari Michii ,  Hajime Maeda

IPC: H01L2302

CPC classification number: H05K1/141 ,  H01L25/105 ,  H01L2225/06551 ,  H01L2225/06555 ,  H01L2225/06572 ,  H01L2225/1005 ,  H01L2225/1029 ,  H01L2225/107 ,  H01L2924/15311 ,  H05K1/144 ,  H05K1/145 ,  H05K1/182 ,  H05K1/183 ,  H05K3/3436 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10386 ,  H05K2201/10515 ,  H05K2201/10689 ,  H05K2203/1572

Abstract: A semiconductor module achieving higher density of the semiconductor module itself as well as of being disposed in an area-efficient manner relative to another electronic component, such as a mother board and the like. The semiconductor module includes a mounting substrate having, on an underside, a solder ball for connecting to an interconnection of a mother board and semiconductor packages mounted in multiple layers on the top side of the mounting substrate and connected to electrodes on the mounting substrate.

Abstract translation: 实现半导体模块本身的更高密度以及相对于诸如母板等的其他电子部件以区域有效的方式设置的半导体模块。 该半导体模块包括安装基板，其在下侧具有用于连接到母板和安装在安装基板的顶侧上的多层的半导体封装的互连的焊球，并连接到安装基板上的电极。

公开(公告)号：US20030232462A1

公开(公告)日：2003-12-18

申请号：US10440590

申请日：2003-05-19

Inventor： Chia Yong Poo ,  Boon Suan Jeung ,  Chua Swee Kwang ,  Low Siu Waf ,  Chan Min Yu ,  Neo Yong Loo

IPC: H01L021/44

CPC classification number: H01L23/13 ,  H01L23/3128 ,  H01L23/49805 ,  H01L25/105 ,  H01L2224/16145 ,  H01L2225/1035 ,  H01L2225/1064 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01087 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/19041 ,  H05K1/141 ,  H05K3/3436 ,  H05K3/3442 ,  H05K3/403 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09181 ,  H05K2201/10727

Abstract: A multichip assembly includes semiconductor devices or semiconductor device components with outer connectors on peripheral edges thereof. The outer connectors are formed by creating via holes along boundary lines between adjacent, unsevered semiconductor devices, or semiconductor device components, then plating or filling the holes with conductive material. When adjacent semiconductor devices or semiconductor device components are severed from one another, the conductive material in each via between the semiconductor devices is bisected. The semiconductor devices and components of the multichip assembly may have different sizes, as well as arrays of outer connectors with differing diameters and pitches. Either or both ends of each outer connector may be electrically connected to another aligned outer connector or contact area of another semiconductor device or component. Assembly in this manner provides a low-profile stacked assembly.

Abstract translation: 多芯片组件包括在其外围边缘上具有外部连接器的半导体器件或半导体器件部件。 外部连接器通过沿相邻的未切割半导体器件或半导体器件部件之间的边界线形成通孔而形成，然后用导电材料电镀或填充孔。 当相邻的半导体器件或半导体器件部件彼此切断时，半导体器件之间的每个通孔中的导电材料被二等分。 多芯片组件的半导体器件和组件可以具有不同的尺寸，以及具有不同直径和间距的外部连接器阵列。 每个外部连接器的一端或两端可以电连接到另一个对准的外部连接器或另一个半导体器件或组件的接触区域。 以这种方式组装提供了低调的堆叠组件。

公开(公告)号：US06535395B2

公开(公告)日：2003-03-18

申请号：US10005464

申请日：2001-12-03

Applicant: Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

Inventor： Joe A. Harrison ,  Edward R. Stanford ,  Thomas G. Ruttan

IPC: H01R1222

CPC classification number: H05K1/141 ,  G06F1/189 ,  H05K1/0263 ,  H05K3/325 ,  H05K3/368 ,  H05K7/1092 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09345 ,  H05K2201/10325 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144

Abstract: A system for delivering power to a processor enables a DC-to-DC converter substrate to be secured to the processor carrier in the Z-axis direction. The ability to assemble the converter to the processor in this way facilitates assembly compared to systems in which the converter is plugged in to the processor carrier in the direction substantially parallel to the surface of the motherboard.

公开(公告)号：US20020100986A1

公开(公告)日：2002-08-01

申请号：US10104826

申请日：2002-03-22

Applicant: Hitachi, Ltd.

Inventor： Tasao Soga ,  Hanae Shimokawa ,  Tetsuya Nakatsuka ,  Kazuma Miura ,  Mikio Negishi ,  Hirokazu Nakajima ,  Tsuneo Endoh

IPC: H01L029/40 ,  H01L023/52 ,  H01L023/48

CPC classification number: H01L24/13 ,  B32B15/01 ,  C22C5/02 ,  C22C9/02 ,  C22C11/06 ,  C22C13/00 ,  H01L21/50 ,  H01L21/56 ,  H01L21/563 ,  H01L23/10 ,  H01L23/3128 ,  H01L23/3677 ,  H01L23/4334 ,  H01L23/4924 ,  H01L23/49513 ,  H01L24/11 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L24/97 ,  H01L25/16 ,  H01L2224/0401 ,  H01L2224/06102 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/29101 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/29294 ,  H01L2224/29298 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81024 ,  H01L2224/81054 ,  H01L2224/81203 ,  H01L2224/81205 ,  H01L2224/8121 ,  H01L2224/81409 ,  H01L2224/81815 ,  H01L2224/8319 ,  H01L2224/83801 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/01088 ,  H01L2924/0132 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/0133 ,  H01L2924/0134 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2924/15738 ,  H01L2924/1576 ,  H01L2924/15787 ,  H01L2924/16152 ,  H01L2924/16315 ,  H01L2924/166 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/141 ,  H05K3/3463 ,  H05K3/3484 ,  H05K2201/0215 ,  H05K2201/045 ,  H05K2201/09572 ,  H05K2201/10636 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2924/01031 ,  H01L2924/01026 ,  H01L2924/3512 ,  H01L2924/00015 ,  H01L2224/29099 ,  H01L2224/29199 ,  H01L2224/29299 ,  H01L2224/2929 ,  H01L2224/83205

Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, etc., and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.

Abstract translation: 形成在半导体器件和衬底之间的接合部包括Cu等的金属球，Sn和金属球的化合物以及金属球通过化合物结合在一起。

公开(公告)号：US5962835A

公开(公告)日：1999-10-05

申请号：US961750

申请日：1997-10-31

Applicant: Cheng-Hung Lin ,  Yu-Ming Ho ,  Tsung-Hsi Ou Lee ,  Hung-Ji Yu

Inventor： Cheng-Hung Lin ,  Yu-Ming Ho ,  Tsung-Hsi Ou Lee ,  Hung-Ji Yu

IPC: H01R12/50 ,  H01R12/72 ,  H05K1/02 ,  H05K1/11 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K5/02 ,  G06K7/06 ,  H05K7/02

CPC classification number: H05K5/0265 ,  H01R23/688 ,  H05K1/141 ,  H05K5/0286 ,  H01R12/721 ,  H05K1/0219 ,  H05K1/0262 ,  H05K1/117 ,  H05K2201/045 ,  H05K2201/049 ,  H05K2201/09954 ,  H05K2201/10189 ,  H05K3/3447 ,  H05K3/366

Abstract: A board adapter for electrically connecting an electrical card connector to a mother board, comprises 68 signal holes, 100 conductive pads, a plurality of signal traces, a first grounding means, a transforming unit and a second grounding contact. The first grounding contact surrounds the signal holes and is electrically connected with a corresponding grounding contact of the electrical connector, for providing the signal holes and the electrical connector with grounding protection. The second grounding contact is alternately juxtaposed with every two of the signal traces for providing grounding protection. The conductive pads are electrically connected with either the signal traces or the grounding contacts. The transforming unit includes two power traces to separately bear two different strength voltage induced currents. When either of the traces bears a corresponding voltage induced current, the other trace can be transformed into a grounding trace to protect the bearing trace.

Abstract translation: 用于将电卡连接器电连接到母板的板适配器包括68个信号孔，100个导电焊盘，多个信号迹线，第一接地装置，变换单元和第二接地触点。 第一接地触点围绕信号孔并与电连接器的对应的接地触点电连接，用于提供信号孔和具有接地保护的电连接器。 第二接地触点与每两个信号迹线交替并置，以提供接地保护。 导电焊盘与信号迹线或接地触点电连接。 变压单元包括两个电源迹线，以分别承受两个不同强度的电压感应电流。 当任一条迹线具有相应的电压感应电流时，其他迹线可以转换为接地迹线以保护轴承轨迹。

公开(公告)号：US5926378A

公开(公告)日：1999-07-20

申请号：US536907

申请日：1995-09-29

Applicant: John R. DeWitt ,  Jay Henry Neer

Inventor： John R. DeWitt ,  Jay Henry Neer

IPC: G06F13/40 ,  H05K1/14 ,  H05K3/36 ,  H05K7/14 ,  G06F13/42 ,  H01R9/09 ,  H01R23/70

CPC classification number: G06F13/409 ,  H05K1/14 ,  H05K7/1445 ,  H05K7/1459 ,  H05K1/141 ,  H05K2201/045 ,  H05K2201/10189 ,  H05K3/366

Abstract: A low-profile computer assembly having a universal footprint on a riser card for mounting peripheral card connectors on the riser card is provided. The peripheral card connectors can be of the edge-card type and can be mounted in pairs, back-to-back, with each connector of the pair extending uniaxially and perpendicularly from opposing sides of a riser card. The two opposing universal footprints on which such a pair of peripheral card connectors are mounted can support a first peripheral card connector having a first bus form factor for a first peripheral bus conforming to a first bus protocol specification and a second, paired peripheral card connector having a second, different bus form factor for a second peripheral bus conforming to a second, different bus protocol specification.

Abstract translation: 提供了一种具有在转接卡上用于将外围卡连接器安装在转接卡上的通用占位面积的低调计算机组件。 外围卡连接器可以是边缘卡类型，并且可以成对地背对背地安装，每对连接器从提升卡的相对侧单向和垂直延伸。 安装这样的一对外围卡连接器的两个相对的通用足迹可以支撑具有第一总线形状因数的第一外围卡连接器，用于符合第一总线协议规范的第一外围总线和具有第二外围卡连接器的第二配对外围卡连接器， 第二种不同的总线形式，用于符合第二种不同总线协议规范的第二外设总线。

公开(公告)号：US5377081A

公开(公告)日：1994-12-27

申请号：US956063

申请日：1992-10-02

Applicant: Tatsuo Bizen ,  Atsushi Inoue ,  You Funada ,  Masao Uno ,  Toshio Hata ,  Kouichi Kongo

Inventor： Tatsuo Bizen ,  Atsushi Inoue ,  You Funada ,  Masao Uno ,  Toshio Hata ,  Kouichi Kongo

IPC: H01L23/00 ,  H01L25/16 ,  H05K1/00 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36 ,  H05K5/00 ,  H05K9/00

CPC classification number: H05K1/141 ,  H01L25/165 ,  H05K5/0091 ,  H05K9/0007 ,  H01L2924/0002 ,  H05K1/0284 ,  H05K2201/045 ,  H05K2201/0999 ,  H05K2201/10371 ,  H05K3/3405 ,  H05K3/3442 ,  H05K3/366 ,  H05K3/368

Abstract: The size precision of a surface mountable electronic part is improved and a production thereof is simplified. The surface mountable electronic part is constructed such that a circuit substrate is housed in a shield case of which an end side is open, and the shield case is a resin case having a shield film. A connection pattern is formed on the inner surface of the case, with one end of the connection pattern being disposed so as to correspond to an external connection land of the circuit substrate, and with the other end of the connection pattern extending to the open end of the case.

Abstract translation: 表面安装电子部件的尺寸精度得到改善并且其生产简化。 可表面安装的电子部件被构造成使得电路基板容纳在端侧敞开的屏蔽壳体中，并且屏蔽壳体是具有屏蔽膜的树脂壳体。 连接图案形成在壳体的内表面上，连接图案的一端设置成与电路基板的外部连接台相对应，连接图案的另一端延伸到开口端 的情况。

公开(公告)号：US4998180A

公开(公告)日：1991-03-05

申请号：US355487

申请日：1989-05-23

Applicant: Scott C. McAuliffe ,  Byron D. Coleman

Inventor： Scott C. McAuliffe ,  Byron D. Coleman

IPC: G06F13/40 ,  H05K1/02 ,  H05K1/14 ,  H05K3/30 ,  H05K3/36 ,  H05K7/14

CPC classification number: H05K7/1451 ,  G06F13/409 ,  H05K1/141 ,  H05K1/0272 ,  H05K2201/045 ,  H05K2201/09063 ,  H05K2201/10409 ,  H05K2201/10515 ,  H05K2201/10606 ,  H05K2201/10689 ,  H05K2201/2036 ,  H05K2203/1572 ,  H05K3/301 ,  H05K3/366 ,  H05K3/368

Abstract: A bus device, such as a memory board, is provided with a mother board and a daughter board mount at a predetermined distance above the surface of the mother board. The daughter board has integrated circuit components, such a memory chips, mounted on both of its sides. Means are provided for connecting the wires on the daughter board with those of the mother board and for connecting the wires on the mother board with the conductors of a system bus. In the preferred embodiment of the invention the distance at which the daughter board is mounted above the surface of the mother board is less than twice the maximum thickness of the electronic components mounted on the side of the memory board facing the mother board. The portion of the mother board under these components contains no electronic components itself. Instead, that portion of the mother board contains at least one ventilation opening to ventilate the components on the side of the daughter board that faces the mother board. The preferred embodiment allows two layers of chips to be mounted in a computer slot in which the maximum permissible extent to which components may stick out from the back of a bus device is too small to allow chips to be mounted on the back of the mother board.

Abstract translation: 诸如存储器板的总线装置在母板表面上方预定距离处设置有母板和子板安装座。 子板具有安装在其两侧的集成电路组件，如存储器芯片。 提供了用于将子板上的电线与母板的电线连接并且用于将母板上的电线与系统总线的导体连接的装置。 在本发明的优选实施例中，子板安装在母板表面之上的距离小于安装在面向母板的存储器板一侧的电子部件的最大厚度的两倍。 这些部件下的母板部分不含电子部件。 相反，母板的该部分包含至少一个通风口，以便使母板侧面上的部件通风。 优选实施例允许两层芯片安装在计算机插槽中，其中组件可能从总线设备的背面伸出的最大允许范围太小以至于不能将芯片安装在母板的背面 。

公开(公告)号：US20240080981A1

公开(公告)日：2024-03-07

申请号：US18261294

申请日：2021-04-11

Applicant: Telefonaktiebolaget LM Ericsson (publ)

Inventor： Donghai Yu ,  Pinghua Duan ,  Qinqin Lu ,  Peng Liu ,  Yunxuan Ma ,  Gongao Xu

IPC: H05K1/14 ,  H05K1/18

CPC classification number: H05K1/141 ,  H05K1/181 ,  H05K2201/045 ,  H05K2201/10984

Abstract: A circuit board assembly (1), comprising a first circuit board (10) and a second circuit board (20) which are electrically connected with each other, and a monolithic substrate (30) configured for supporting a power component and comprising a first contact surface (31) that is fixedly connected to and forms a thermal contact with the second circuit board (20), the circuit board assembly being characterized in that, the substrate (30) further comprises a second contact surface (32) that is fixedly connected to the first circuit board (10) and forms a thermal contact with the first circuit board (10) so that the substrate functions as an extension of the first circuit board to support the second circuit board. A radio unit comprising a circuit board assembly (1) is also disclosed.

公开(公告)号：US09807882B1

公开(公告)日：2017-10-31

申请号：US15239751

申请日：2016-08-17

Applicant: QUALCOMM Incorporated

Inventor： David Francis Berdy ,  Changhan Hobie Yun ,  Niranjan Sunil Mudakatte ,  Mario Francisco Velez ,  Chengjie Zuo ,  Jonghae Kim

IPC: H01L23/48 ,  H05K1/11 ,  H05K3/40 ,  H05K3/30 ,  H05K1/03 ,  H05K1/18 ,  H01F27/28 ,  H05K3/06 ,  H03H7/01 ,  H03H7/46 ,  H01L49/02 ,  H01L23/66 ,  H01Q1/48 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/24

CPC classification number: H05K1/181 ,  H01F27/2804 ,  H01L23/49822 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/645 ,  H01L23/66 ,  H01L24/06 ,  H01L28/10 ,  H01L2223/6672 ,  H01L2223/6677 ,  H01L2224/16225 ,  H01Q1/241 ,  H01Q1/36 ,  H01Q1/38 ,  H01Q1/48 ,  H03H7/0115 ,  H03H7/0138 ,  H03H7/46 ,  H05K1/0224 ,  H05K1/0271 ,  H05K1/144 ,  H05K3/06 ,  H05K3/303 ,  H05K2201/041 ,  H05K2201/045 ,  H05K2201/0715 ,  H05K2201/09136 ,  H05K2201/1003 ,  H05K2201/10378 ,  H05K2201/10674

Abstract: An integrated circuit (IC) device may include a first substrate having an inductor ground plane in a conductive layer of the first substrate. The integrated circuit may also include a first inductor in a passive device layer of a second substrate that is supported by the first substrate. A shape of the inductor ground plane may substantially correspond to a silhouette of the first inductor.