公开(公告)号：US20020189849A1

公开(公告)日：2002-12-19

申请号：US10108628

申请日：2002-03-29

Applicant: IBIDEN Co., Ltd.

Inventor： Naohiro Hirose ,  Takashi Kariya ,  Yoji Mori

IPC: H05K007/06

CPC classification number: H01R9/09 ,  H01L23/12 ,  H01L23/48 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H05K1/0256 ,  H05K1/0263 ,  H05K1/0265 ,  H05K1/0271 ,  H05K1/113 ,  H05K1/115 ,  H05K1/116 ,  H05K3/184 ,  H05K3/241 ,  H05K3/382 ,  H05K3/4602 ,  H05K3/4661 ,  H05K2201/09227 ,  H05K2201/09236 ,  H05K2201/09254 ,  H05K2201/09272 ,  H05K2201/09454 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/09627 ,  H05K2201/09727 ,  H05K2201/09781 ,  H05K2201/10734 ,  H05K2203/0594 ,  Y10T29/49155 ,  Y10T29/49194 ,  Y10T428/31504

Abstract: A filet F is added to a portion constituting a corner portion C equal to or smaller than 90null in a crossing portion X of wiring patterns 58b, 58c and 58d, and a wiring pattern 58 is formed. Since the filet F is added, the wiring patterns are not made thin and are not disconnected in the crossing portion X. Further, since there is no stress concentrated to the crossing portion X, disconnection is not caused in the wiring patterns and no air bubbles are left between the crossing portion X of the wiring patterns and an interlayer resin insulating layer so that reliability of a printed wiring board is improved.

Abstract translation: 在布线图案58b，58c和58d的交叉部分X中，在构成拐角部分C等于或小于90°的部分加上一个纸条F，并形成布线图案58。 由于添加了纸张F，所以布线图案不会变薄，并且在交叉部分X中不会断开。另外，由于不会对交叉部分X集中的应力，因此布线图案中不会导致断线，也不会产生气泡 留在布线图案的交叉部分X和层间树脂绝缘层之间，从而提高了印刷线路板的可靠性

公开(公告)号：US06489574B1

公开(公告)日：2002-12-03

申请号：US09702763

申请日：2000-11-01

Applicant: Toru Otaki ,  Hideho Inagawa ,  Toru Osaka

Inventor： Toru Otaki ,  Hideho Inagawa ,  Toru Osaka

IPC: H05K111

CPC classification number: H05K1/112 ,  H05K2201/09227 ,  H05K2201/09336 ,  H05K2201/0939 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A printed wiring board having assembled thereon a grid array type package, a multi-terminal device with many terminals arranged in matrix, is provided, through first signal connection holes, signal lines, and second connection holes, with many numbers of lands divided into plural blocks, being arranged in matrix on a first layer to connect each terminal of the multi-terminal device correspondingly, signal line patterns connected with many lands, and drawn out in the same direction per block, and first signal patterns from lands positioned on the innermost line of many lands. Then, the wiring patterns of the signal lines are drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it easier for the printed wiring board to effectuate wiring connections without making them complicated or increasing the number of layers of the printed wiring board. Also, with the provision of ground patterns that surround signal lines, it is made possible to reduce unwanted radiant, as well as to suppress the occurrence of malfunctions of electronic equipment due to reflections and ground bounces.

Abstract translation: 在其上组装有格栅阵列型封装的印刷电路板，具有以矩阵形式布置的许多端子的多端子装置，通过第一信号连接孔，信号线和第二连接孔提供，其中多个焊盘被分成多个 块，以矩阵形式布置在第一层上，以相应地连接多终端设备的每个终端，与许多焊盘相连并沿与每块相同的方向拉出的信号线图案，以及位于最内层的焊盘的第一信号图案 许多土地线。 然后，信号线的布线图案从栅格阵列型封装的组装面上的矩阵状的多个区域中规则地拉出，使得印刷布线板更容易实现布线连接而不使其复杂或增加数量 的印刷线路板的层。 而且，通过提供围绕信号线的接地图案，可以减少不必要的辐射，并且抑制由于反射和地面反弹引起的电子设备故障的发生。

公开(公告)号：US06414248B1

公开(公告)日：2002-07-02

申请号：US09679252

申请日：2000-10-04

Applicant: Lance L. Sundstrom

Inventor： Lance L. Sundstrom

IPC: H05K116

CPC classification number: H05K1/141 ,  H05K3/28 ,  H05K3/3436 ,  H05K3/368 ,  H05K2201/049 ,  H05K2201/09481 ,  H05K2201/09627 ,  H05K2201/0979 ,  H05K2201/10378 ,  H05K2201/10734 ,  Y02P70/613 ,  Y10T29/49149

Abstract: Parallel surfaces are interfacially mechanically bonded and optionally electrically, and/or thermally connected using an interposer fabricated from a flexible laminates, such as flex PWB. The bond/connection points for the device made on one side of the interposer are displaced in the X and Y axis from the bond/connection points on the other or obverse side for the interposer and the board. The optional electrical/thermal connection through the interposer is made through one or more traces and vias in the flex board.

Abstract translation: 使用由柔性层压板（例如柔性板）制成的插入件，平行表面被界面机械地接合并且任选地电气和/或热连接。 在插入器的一侧上形成的器件的接合/连接点在X和Y轴上从用于插入器和板的另一侧或正面的接合/连接点移位。 通过插入器的可选电/热连接通过柔性板中的一个或多个迹线和通孔进行。

公开(公告)号：US06407343B1

公开(公告)日：2002-06-18

申请号：US09615942

申请日：2000-07-13

Applicant: Shinji Tanaka

Inventor： Shinji Tanaka

IPC: H05K111

CPC classification number: H05K1/114 ,  H01L23/5384 ,  H01L23/5386 ,  H01L2224/16225 ,  H01L2924/15312 ,  H05K1/0289 ,  H05K1/115 ,  H05K2201/09627 ,  H05K2201/09709 ,  H05K2201/09854 ,  H05K2201/10674

Abstract: A wiring layer on which X-directional signal lines 20 to 22 are arranged is formed on a multilayer board. Rectangular power-source conductive patterns 10c are arranged each in which via holes 12c are formed longitudinally or in the wiring direction of the X-directional signal lines 20 to 22. The area (hatched with broken lines) acts as a wiring channel for the X-directional signal line 22.

Abstract translation: 在多层基板上形成配置有X方向信号线20〜22的布线层。 矩形电源导体图案10c布置成沿X方向信号线20至22的纵向或布线方向形成有通孔12c。用虚线划线的区域用作X的布线通道 双向信号线22。

公开(公告)号：US06021564A

公开(公告)日：2000-02-08

申请号：US159140

申请日：1998-09-23

Applicant: David A. Hanson

Inventor： David A. Hanson

IPC: H01L23/12 ,  H01L21/48 ,  H01L23/498 ,  H01L23/538 ,  H01L23/66 ,  H05K1/11 ,  H01K3/10

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/66 ,  H05K1/115 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K2201/0792 ,  H05K2201/09509 ,  H05K2201/09627 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A method of making a low inductance conductive via in a laminated substrate by providing a first conductive layer. A first dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the first dielectric layer. A first conductive path is formed in the first conductive layer extending along a first route between a first node and a second node. A first conductive blind-via is connected to the first conductive path at the second node, with the first-blind via being formed in the first dielectric layer at the second node. Lastly, a second conductive path is formed in the second conductive layer that is connected to the first blind via. The second conductive path extends between a third node and the first blind via along a second route. The second route corresponds identically to at least a portion of the first route.

Abstract translation: 一种通过提供第一导电层在叠层基板中制造低电感导电通孔的方法。 在第一导电层上形成第一电介质层。 在第一电介质层上形成第二导电层。 第一导电路径形成在沿着第一节点和第二节点之间的第一路由延伸的第一导电层中。 第一导电盲通孔在第二节点处连接到第一导电路径，其中第一通孔形成在第二节点处的第一介电层中。 最后，在连接到第一盲通孔的第二导电层中形成第二导电路径。 第二导电路径沿着第二路径在第三节点和第一盲孔之间延伸。 第二路线与第一路线的至少一部分相同。

公开(公告)号：US5451885A

公开(公告)日：1995-09-19

申请号：US373916

申请日：1995-01-17

Applicant: Stephen M. Birch ,  Gerard M. Gavrel ,  Zaffar I. Memon

Inventor： Stephen M. Birch ,  Gerard M. Gavrel ,  Zaffar I. Memon

IPC: G01R31/28 ,  H05K1/02 ,  H05K3/42 ,  G01R31/02

CPC classification number: G01R31/2805 ,  G01R31/2817 ,  G01R31/2818 ,  H05K1/0212 ,  H05K1/0266 ,  H05K1/0268 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/10151 ,  H05K2203/1115 ,  H05K2203/1194 ,  H05K2203/162 ,  H05K3/429

Abstract: This disclosure describes an Interconnect Stress Testing (IST) system and a printed wiring board test coupon which is used with the IST system. The system includes a computer device and a cabinet which is used for mounting the test coupon as well as housing a number of the other components that make up the system. During a pre-cycling phase, the system determines the correct current that should be passed through the coupon in order to heat it to a predetermined temperature. After that test current value is determined the system actually stress tests the coupon by passing the determined test current through the coupon. It does so for a selected number of cycles, and monitors resistance changes in the coupon during testing while recording test data. This disclosure also describes the test coupon, which is designed to uniformly dissipate the heat created during stress cycling.

Abstract translation: 本公开描述了与IST系统一起使用的互连压力测试（IST）系统和印刷线路板测试券。 该系统包括一个计算机设备和一个柜子，用于安装测试件以及容纳构成系统的其他组件。 在预循环阶段期间，系统确定应该通过试样的正确电流，以将其加热到预定温度。 在该测试之后，确定当前值，系统实际上通过将确定的测试电流通过优惠券来测试优惠券。 它在选定的周期内执行此操作，并在记录测试数据的同时监测测试期间优惠券的电阻变化。 本公开还描述了测试试样，其被设计成均匀地消散在应力循环期间产生的热量。

公开(公告)号：US5378314A

公开(公告)日：1995-01-03

申请号：US77298

申请日：1993-06-15

Applicant: Walter Schmidt ,  Marco Martinelli

Inventor： Walter Schmidt ,  Marco Martinelli

IPC: C23F1/00 ,  H05K1/00 ,  H05K1/05 ,  H05K1/11 ,  H05K3/00 ,  H05K3/38 ,  H05K3/40 ,  H05K3/42 ,  H05K3/46 ,  B44C1/22 ,  B29C37/00

CPC classification number: H05K3/42 ,  H05K1/115 ,  H05K3/0041 ,  H05K3/4084 ,  H05K1/0287 ,  H05K1/0289 ,  H05K1/0393 ,  H05K1/05 ,  H05K2201/0195 ,  H05K2201/0355 ,  H05K2201/0394 ,  H05K2201/0397 ,  H05K2201/066 ,  H05K2201/0909 ,  H05K2201/09327 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09781 ,  H05K2201/09836 ,  H05K2201/09945 ,  H05K2201/10666 ,  H05K2203/0554 ,  H05K2203/0746 ,  H05K2203/1184 ,  H05K2203/1545 ,  H05K2203/1572 ,  H05K3/0061 ,  H05K3/0064 ,  H05K3/0097 ,  H05K3/386 ,  H05K3/427 ,  H05K3/429 ,  H05K3/4652

Abstract: A method for producing aligned passages through substrate materials, in which the projection of the inlet and outlet openings does not coincide, uses displaced application of etching windows on opposite sides and corresponding pronounced under-etching of these windows. By applying displaced etching windows on both sides of the substrate and through-etching the substrate through these windows, `oblique` passages are obtained through the substrate. By a suitable location of the windows it is also possible to produce branched passages with more than one outlet opening.

Abstract translation: 用于产生通过基底材料的对准的通道的方法，其中入口和出口的突出部不重合，使用在相对侧上移动施加蚀刻窗口并且对应于这些窗口的相当明显的下蚀刻。 通过在基板的两面上施加位移蚀刻窗口，并通过这些窗口对基板进行蚀刻，通过基板获得“倾斜”通道。 通过窗口的合适位置，也可以产生具有多于一个出口开口的分支通道。

公开(公告)号：US5320894A

公开(公告)日：1994-06-14

申请号：US702326

申请日：1991-05-20

Applicant: Shinichi Hasegawa

Inventor： Shinichi Hasegawa

IPC: H05K3/46 ,  H01L23/538 ,  H05K1/03 ,  H05K1/11 ,  B32B9/00

CPC classification number: H01L23/538 ,  H01L23/5384 ,  H05K1/115 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/0979 ,  Y10S428/901 ,  Y10T428/24322 ,  Y10T428/24917 ,  Y10T428/24926

Abstract: A multilayer interconnection substrate having, e.g., first to third power interconnections provided with first to third interconnection layers. A first insulating layer is provided between the first and second interconnection layers, and a second insulating layer is provided between the second and third interconnection layers. A plurality of first via holes are provided at said first insulating layer and connect the first and second power interconnections and a plurality of second via holes are provided at said second insulating layer with their position being shifted from that of the first via holes and connect the second and third power interconnection.

Abstract translation: 具有例如设置有第一至第三互连层的第一至第三电源互连的多层互连衬底。 第一绝缘层设置在第一和第二互连层之间，第二绝缘层设置在第二和第三互连层之间。 多个第一通孔设置在所述第一绝缘层处并且连接第一和第二电源互连，并且多个第二通孔设置在所述第二绝缘层处，其位置与第一通孔的位置相连， 第二和第三电力互连。

公开(公告)号：US5036431A

公开(公告)日：1991-07-30

申请号：US393013

申请日：1989-08-11

Applicant: Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

Inventor： Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K1/114 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10871 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/368 ,  H05K3/4652

Abstract: A package for surface-mounted components according to the present invention includes a first board which includes contact portions formed on a front face side thereof for mounting the components to be surface-mounted thereon, and first through-holes electrically contiguous with the contact portions; a second board includes conductor pins provided on a rear face side thereof for establishing continuity with another board and second through-holes electrically contiguous with the conductor pins; and a conductor layer interposed between the first and second boards by which the first through-holes in the first board side and the second through-holes in the second board side are mutually electrically connected.

Abstract translation: 根据本发明的用于表面安装部件的包装包括第一板，其包括形成在其正面侧上的接触部分，用于安装要表面安装的部件，以及与接触部分电连接的第一通孔; 第二板包括设置在其背面侧的导体销，用于与另一个板形成连续性，并且与导体引脚电连接的第二通孔; 以及介于第一和第二板之间的导体层，第一板侧的第一通孔和第二板侧的第二通孔相互电连接。

公开(公告)号：US4613924A

公开(公告)日：1986-09-23

申请号：US671093

申请日：1984-11-13

Applicant: Roland Brault

Inventor： Roland Brault

IPC: H05K1/00 ,  H05K1/11 ,  H05K3/42 ,  H05K1/14

CPC classification number: H05K1/112 ,  H05K1/0295 ,  H05K1/0298 ,  H05K2201/09227 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09954 ,  H05K2201/10689 ,  H05K3/429

Abstract: A printed card with impressions comprising several rows of conducting holes spaced apart by a multiple of a constant pitch and disposed in a repetitive pattern, each conducting hole being connected to a wiring stud provided on the wiring face within the pattern. Furthermore, the holes of some adjacent rows are connected to wiring tracks provided on the component face of the card and the holes of other adjacent rows are connected together and connected to the same wiring stud.

Abstract translation: 一种具有印刷的印刷卡，其具有由多个恒定间距间隔开并以重复图案布置的多排导电孔，每个导电孔连接到设置在图案内的布线面上的布线螺柱。 此外，一些相邻行的孔连接到设置在卡的组件面上的布线轨道，并且其他相邻行的孔连接在一起并连接到同一布线柱。