公开(公告)号：US09204550B2

公开(公告)日：2015-12-01

申请号：US13633074

申请日：2012-10-01

Applicant: SMART Modular Technologies, Inc.

Inventor： Victor Mahran ,  Robert S. Pauley, Jr.

IPC: G06F1/16 ,  H05K5/00 ,  H05K7/00 ,  H05K7/20 ,  H01L23/48 ,  H01R12/00 ,  H05K1/14 ,  H05K7/14 ,  H05K1/02 ,  G06F1/20 ,  G11C5/02

CPC classification number: G06F1/185 ,  G06F1/20 ,  G11C5/025 ,  H05K1/0209 ,  H05K1/144 ,  H05K1/145 ,  H05K7/1431 ,  H05K2201/042 ,  H05K2201/10159 ,  H05K2201/10303 ,  H05K2201/10378 ,  H05K2201/10409 ,  Y10T29/4913

Abstract: A method of manufacture of an enhanced capacity memory system includes: providing a dual in-line memory module carrier having a memory module and an integrated memory buffer coupled to the memory module; coupling a memory expansion board, having a supplementary memory module, to the dual in-line memory module carrier including attaching a bridge transposer; and providing a system interface connector coupled to the integrated memory buffer and the bridge transposer for controlling the memory module, the supplementary memory module, or a combination thereof.

Abstract translation: 一种制造增强容量存储器系统的方法包括：提供具有存储器模块和耦合到存储器模块的集成存储器缓冲器的双列直插存储器模块载体; 将具有辅助存储器模块的存储器扩展板耦合到双列直插式存储器模块载体，包括附接桥式变压器; 并且提供耦合到集成存储器缓冲器的系统接口连接器和用于控制存储器模块，辅助存储器模块或其组合的桥接转换器。

公开(公告)号：US09173293B2

公开(公告)日：2015-10-27

申请号：US13406892

申请日：2012-02-28

Applicant: Yasuyuki Nagahara ,  Isao Ozawa

Inventor： Yasuyuki Nagahara ,  Isao Ozawa

IPC: G06F12/00 ,  H05K1/18 ,  G06F17/50 ,  G06F12/02 ,  G11C29/48 ,  G11C5/04 ,  G11C16/00 ,  G11C29/56 ,  H05K1/02

CPC classification number: G11C5/025 ,  G06F12/0246 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5077 ,  G06F17/5081 ,  G11C5/04 ,  G11C16/00 ,  G11C29/48 ,  G11C2029/5602 ,  H05K1/0268 ,  H05K1/181 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10545 ,  H05K2203/162 ,  Y02P70/611

Abstract: According to the embodiments, there are provided semiconductor memories that are mounted individually on two sides of a mounting board; a controller that is mounted either on an obverse side or a reverse side of the mounting board, and performs read and write control of the semiconductor memories; and a connector that is deviated in a lateral direction from the controller so as not to overlap the controller, is mounted either on the obverse side or the reverse side of the mounting board, and transfers a signal exchanged between the controller and outside.

Abstract translation: 根据实施例，提供了分别安装在安装板的两侧上的半导体存储器; 控制器，其安装在安装板的正面或反面上，并且执行对半导体存储器的读取和写入控制; 并且在控制器的横向上偏离控制器而不与控制器重叠的连接器安装在安装板的正面或反面上，并且传送在控制器和外部之间交换的信号。

公开(公告)号：US20150264817A1

公开(公告)日：2015-09-17

申请号：US14723520

申请日：2015-05-28

Applicant: IBIDEN CO., LTD.

Inventor： Makoto TERUI ,  Daiki KOMATSU ,  Masatoshi KUNIEDA ,  Takashi KARIYA

IPC: H05K3/30 ,  H01L23/00 ,  H05K3/32 ,  H05K3/20 ,  H05K3/10 ,  H05K3/46 ,  H01L25/00 ,  H01L23/498

CPC classification number: H05K3/305 ,  H01L21/563 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5382 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/03 ,  H01L24/16 ,  H01L24/81 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81192 ,  H01L2924/12042 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15311 ,  H05K1/115 ,  H05K3/10 ,  H05K3/103 ,  H05K3/20 ,  H05K3/32 ,  H05K3/4602 ,  H05K3/4658 ,  H05K3/4694 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/1053 ,  Y10T29/49128 ,  Y10T29/49165 ,  H01L2924/00 ,  H01L2924/014

Abstract: A method for manufacturing a wiring board includes positioning on a first insulation layer a wiring structure including an insulation layer and conductive patterns formed on the insulation layer, forming a second insulation layer on the first insulation layer and the wiring structure such that the wiring structure is interposed between the first insulation layer and the second insulation layer, forming a via conductor through the second insulation layer, and forming conductive patterns on the second insulation layer such that one of the conductive patterns on the second insulation layer is connected to the via conductor in the second insulation layer.

Abstract translation: 一种布线基板的制造方法，其特征在于，在第一绝缘层上具有绝缘层和形成于绝缘层上的导电图案的布线结构，在第一绝缘层和布线结构上形成第二绝缘层，使布线结构为 插入在第一绝缘层和第二绝缘层之间，通过第二绝缘层形成通孔导体，并且在第二绝缘层上形成导电图案，使得第二绝缘层上的导电图案之一连接到通孔导体 第二绝缘层。

公开(公告)号：US20150257255A1

公开(公告)日：2015-09-10

申请号：US14719321

申请日：2015-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC: H05K1/02 ,  G11C29/04 ,  G11C5/02 ,  G11C5/06 ,  H05K1/11 ,  H05K1/18

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US09123555B2

公开(公告)日：2015-09-01

申请号：US14063119

申请日：2013-10-25

Applicant: Invensas Corporation

Inventor： Richard Dewitt Crisp ,  Belgacem Haba ,  Wael Zohni

IPC: H01L23/02 ,  H01L25/065 ,  H01L23/00 ,  H01L23/50

CPC classification number: H01L25/0657 ,  H01L23/12 ,  H01L23/13 ,  H01L23/50 ,  H01L24/06 ,  H01L24/09 ,  H01L2224/023 ,  H01L2224/04042 ,  H01L2224/06136 ,  H01L2224/09151 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/01322 ,  H01L2924/14361 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K1/0248 ,  H05K1/112 ,  H05K1/181 ,  H05K3/3415 ,  H05K2201/10159 ,  Y02P70/611 ,  H01L2924/00

Abstract: A microelectronic package has a dielectric element with first and second parallel apertures. A first microelectronic element has contacts overlying the first aperture, and a second microelectronic element has contacts overlying the second aperture. The second microelectronic element can overlie a rear face of the first microelectronic element and the same surface of the dielectric element as the first microelectronic element. First terminals on a second surface of the dielectric element between said first and second apertures can be configured to carry all data signals for read and write access to memory locations within the first and second microelectronic elements.

Abstract translation: 微电子封装具有带有第一和第二平行孔的电介质元件。 第一微电子元件具有覆盖第一孔的触点，并且第二微电子元件具有覆盖第二孔的触点。 第二微电子元件可以覆盖第一微电子元件的后表面和与第一微电子元件相同的介质元件的表面。 位于所述第一和第二孔之间的电介质元件的第二表面上的第一端子可被配置为承载用于对第一和第二微电子元件内的存储器位置的读取和写入访问的所有数据信号。

公开(公告)号：US20150245533A1

公开(公告)日：2015-08-27

申请号：US14275690

申请日：2014-05-12

Applicant: SanDisk Enterprise IP LLC

Inventor： David A. Wright ,  David Dean ,  Robert W. Ellis

IPC: H05K7/20 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K7/20709 ,  H05K1/0203 ,  H05K1/0207 ,  H05K1/0254 ,  H05K1/0259 ,  H05K1/181 ,  H05K7/1489 ,  H05K7/2039 ,  H05K7/205 ,  H05K2201/066 ,  H05K2201/10159

Abstract: Various embodiments described herein include systems, methods and/or devices used to dissipate heat generated by electronic components in an electronic system (e.g., a memory system that includes closely spaced memory modules). In one aspect, an electronic system includes a substrate, at least one electronic component, and a heat sink. The at least one electronic component is mechanically coupled to the substrate and thermally coupled to a ground plane of the substrate, such that heat generated by the at least one electronic component is dissipated at least partially to the ground plane of the substrate. The heat sink is mechanically coupled to an edge of the substrate, and thermally coupled to the ground plane of the substrate to at least partially dissipate the heat generated by the at least one electronic component. In some embodiments, the heat sink further includes an attachment structure, a tab and a plurality of heat dissipaters.

Abstract translation: 本文描述的各种实施例包括用于消散由电子系统（例如，包括紧密间隔的存储器模块的存储器系统）中的电子部件产生的热的系统，方法和/或设备。 一方面，电子系统包括基板，至少一个电子部件和散热器。 所述至少一个电子部件机械耦合到所述基板并且热耦合到所述基板的接地平面，使得由所述至少一个电子部件产生的热量至少部分地被耗散到所述基板的接地平面。 散热器机械耦合到衬底的边缘，并且热耦合到衬底的接地平面，以至少部分地耗散由至少一个电子部件产生的热量。 在一些实施例中，散热器还包括附接结构，突片和多个散热器。

公开(公告)号：US20150243371A1

公开(公告)日：2015-08-27

申请号：US14705971

申请日：2015-05-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC: G11C29/12 ,  G01R31/28 ,  H01L25/065 ,  H01L23/498 ,  G11C5/02 ,  H01L25/18

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US20150208510A1

公开(公告)日：2015-07-23

申请号：US14158310

申请日：2014-01-17

Applicant: Freescale Semiconductor, Inc.

Inventor： Perry H. Pelley ,  Michael B. McShane ,  Tim V. Pham

IPC: H05K1/18 ,  H05K1/11

CPC classification number: H05K1/181 ,  G11C5/063 ,  H01L23/5384 ,  H01L23/5385 ,  H01L25/0652 ,  H01L25/10 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06562 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/1434 ,  H05K3/3415 ,  H05K2201/097 ,  H05K2201/10159 ,  H05K2201/10378 ,  H05K2201/10545 ,  Y02P70/611 ,  H01L2924/014 ,  H01L2924/00014

Abstract: A low profile strip dual in-line memory module (200) includes a passive interposer support structure (90) with patterned openings (91-97) formed between opposing top and bottom surfaces, a plurality of memory chips (D1-D8) attached to the top and bottom surfaces, and vertical solder ball conductors (98) extending through the patterned openings to electrically connect the plurality of memory chips, where each memory chip has an attachment surface facing the passive interposer structure and a patterned array of horizontal conductors (e.g., 82-86) formed on the attachment surface with contact pads electrically connected to the plurality of vertical conductors to define at least one bus conductor that is electrically connected to each memory die in the first and second plurality of memory die.

Abstract translation: 低剖面条双列直插式存储器模块（200）包括：被动中插支撑结构（90），其具有形成在相对的顶表面和底表面之间的图案化开口（91-97）;多个存储芯片（D1-D8） 顶表面和底表面以及垂直焊球导体（98），其延伸穿过图案化的开口以电连接多个存储器芯片，其中每个存储器芯片具有面向无源插入器结构的附接表面和水平导体的图案化阵列（例如， ，82-86），其形成在所述附接表面上，所述接触垫电连接到所述多个垂直导体，以限定电连接到所述第一和第二多个存储器管芯中的每个存储器管芯的至少一个总线导体。

公开(公告)号：US20150177779A1

公开(公告)日：2015-06-25

申请号：US14544875

申请日：2015-02-27

Applicant: James E. Clayton ,  Zakaryae Fathi

Inventor： James E. Clayton ,  Zakaryae Fathi

IPC: G06F1/16 ,  H05K1/18 ,  H05K1/02

CPC classification number: G06F1/16 ,  G06F1/184 ,  G06F1/185 ,  H01R12/62 ,  H05K1/028 ,  H05K1/118 ,  H05K1/147 ,  H05K1/181 ,  H05K3/366 ,  H05K2201/046 ,  H05K2201/09481 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10409 ,  H05K2201/10545

Abstract: An electrical interconnection system comprises a bifurcated, multilayer flex circuit having electrode pads on the inner surfaces of the bifurcation. Electronic components are mounted on one or both sides of the flex circuit by conventional means. When the bifurcation is spread apart, the electrode pads are alignable with respective contacts on a printed circuit board. After bonding the pads to the contacts by soldering, conductive adhesive, or other means, a secure electrical connection is maintained while still allowing the flex circuit to bend somewhat from side to side, creating additional design options not available with rigidly mounted components and modules.

Abstract translation: 电互连系统包括在分叉的内表面上具有电极焊盘的分叉的多层柔性电路。 电子部件通过常规方式安装在柔性电路的一侧或两侧。 当分叉分开时，电极焊盘可与印刷电路板上的各个触点对准。 在通过焊接，导电粘合剂或其他方式将焊盘接合到触点之后，保持牢固的电连接，同时仍然允许柔性电路从一侧到另一侧弯曲一些，从而产生不具有刚性安装的部件和模块的附加设计选项。

公开(公告)号：US09054466B2

公开(公告)日：2015-06-09

申请号：US13586981

申请日：2012-08-16

Applicant: David S. Lin

Inventor： David S. Lin

IPC: H05K7/00 ,  H01R12/71 ,  H01R12/73 ,  H05K1/14 ,  H05K3/32 ,  H05K3/34

CPC classification number: H01R12/712 ,  H01R12/73 ,  H05K1/141 ,  H05K3/32 ,  H05K3/3436 ,  H05K2201/042 ,  H05K2201/049 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10962 ,  H05K2203/176

Abstract: An integrated circuit assembly includes a main board unit mounted fixedly on and connected electrically to an external circuit board, a daughter board unit disposed on and connected detachably to the main board unit, and an integrated circuit device mounted fixedly on and connected electrically to the daughter board unit. When the daughter board unit is connected to the main board unit, the integrated circuit device is connected electrically to the external circuit board via the main board unit and the daughter board unit.

Abstract translation: 集成电路组件包括固定地安装在电连接到外部电路板的主板单元，以及可拆卸地设置在主板单元上并且可拆卸地连接到主板单元的子板单元，以及集成电路装置，其固定地安装在电子上并连接到该女儿 板单位。 当子板单元连接到主板单元时，集成电路器件经由主板单元和子板单元电连接到外部电路板。