公开(公告)号：US20240030917A1

公开(公告)日：2024-01-25

申请号：US17932075

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US20230418705A1

公开(公告)日：2023-12-28

申请号：US18459215

申请日：2023-08-31

Applicant: NVIDIA Corp.

Inventor： Gautam Bhatia ,  Sunil Sudhakaran ,  Kyutaeg Oh

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1004 ,  G06F11/0787 ,  G06F11/1068

Abstract: A transceiver configured to communicate a burst of data bits and meta-data bits for the data bits includes data channels, auxiliary data channels, and at least one error correction channel. The transceiver includes an encoder that applies 11b7s encoding to a first number of the data bits to generate first PAM-3 symbols on some or all of the communication channels, and that applies 3b2s encoding to a second number of the data bits to generate second PAM-3 symbols on at least some of the communication channels.

公开(公告)号：US20230352081A1

公开(公告)日：2023-11-02

申请号：US17730379

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Jiwang Lee ,  Jaewon Lee ,  Hsuche Nee ,  Po-Chien Chiang ,  Wen-Hung Lo ,  Abhishek Dhir ,  Michael Ivan Halfen ,  CHUNJEN SU

IPC: G11C11/4093 ,  H03K17/687

CPC classification number: G11C11/4093 ,  H03K17/6874

Abstract: A multi-rank circuit system utilizing a shared IO channel includes a first stage of multiple selectors coupled to input multiple digital busses, and a second stage including one or more selectors coupled to receive outputs of the first stage of selectors and to individually select one of the outputs of the first stage of selectors to one or more control circuits for IO circuits of the ranks. The system switches one of the ranks to be an active rank on the shared IO channel, and operates the first stage of selectors to select one of the digital busses to the second stage of selectors in advance of switching a next active rank to the shared IO channel.

公开(公告)号：US20230352078A1

公开(公告)日：2023-11-02

申请号：US17730423

申请日：2022-04-27

Applicant: NVIDIA Corp.

Inventor： Jiwang Lee ,  Jaewon Lee ,  Wen-Hung Lo ,  Michael Ivan Halfen ,  Abhishek Dhir ,  Hsuche Nee ,  Po-Chien Chiang

IPC: G11C11/4074

CPC classification number: G11C11/4074

Abstract: The differential voltage output from a first reference voltage generator of a multi-rank circuit is trained on multiple ranks of the multi-rank circuit. Multiple local reference voltage generators are trained to generate reference voltages for communication on the individual ranks, where the reference voltages output by the local reference voltage generators fall within a range of the differential voltage output.

公开(公告)号：US11750192B2

公开(公告)日：2023-09-05

申请号：US17546438

申请日：2021-12-09

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Yan He

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

公开(公告)号：US11687679B2

公开(公告)日：2023-06-27

申请号：US18046275

申请日：2022-10-13

Applicant: NVIDIA Corp.

Inventor： Nikola Nedovic ,  Sudhir Shrikantha Kudva

IPC: G06F21/75 ,  H02M1/44 ,  H02M1/08 ,  H02M3/155

CPC classification number: G06F21/755 ,  H02M1/08 ,  H02M1/44 ,  H02M3/155

Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

公开(公告)号：US20230161467A1

公开(公告)日：2023-05-25

申请号：US17954872

申请日：2022-09-28

Applicant: NVIDIA Corp.

Inventor： Xun Huang ,  Ting Wang ,  Arun Mallya ,  Ming-Yu Liu

IPC: G06F3/04845 ,  G06T11/60 ,  G06F3/04847

CPC classification number: G06F3/04845 ,  G06T11/60 ,  G06F3/04847

Abstract: Techniques are described for synthesizing images with multiple input modalities. According to some embodiments, a user interface is displayed. The user interface comprises an input area operable to display one or more inputs corresponding to one or more input modalities, an output area operable to display an output image generated based on the one or more inputs, and at least one control operable to select which ones of the one or more input modalities should influence generation of the output image.

公开(公告)号：US11651194B2

公开(公告)日：2023-05-16

申请号：US16859585

申请日：2020-04-27

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06F16/901 ,  G06F17/16 ,  G06N3/045

CPC classification number: G06N3/045 ,  G06F16/9024 ,  G06F17/16

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US11645533B2

公开(公告)日：2023-05-09

申请号：US15929242

申请日：2020-03-17

Applicant: NVIDIA Corp.

Inventor： Zhiyao Xie ,  Haoxing Ren ,  Brucek Khailany ,  Sheng Ye

IPC: G06N3/084 ,  G06F30/398 ,  G06N3/04 ,  G06F119/06

CPC classification number: G06N3/084 ,  G06F30/398 ,  G06N3/04 ,  G06F2119/06

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

公开(公告)号：US11632275B2

公开(公告)日：2023-04-18

申请号：US17243035

申请日：2021-04-28

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/34 ,  H04L25/49 ,  H04B1/00

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.