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101.
公开(公告)号:US09915778B2
公开(公告)日:2018-03-13
申请号:US15038349
申请日:2015-11-16
IPC: G09G3/3225 , F21V8/00 , H05B33/08 , H05K1/02
CPC classification number: G02B6/009 , G02B6/0068 , G02B6/0073 , H05B33/0815 , H05B33/0821 , H05B33/0845 , H05B33/089 , H05K1/028 , H05K1/189 , H05K2201/09409 , H05K2201/09709 , H05K2201/10106 , Y02B20/346
Abstract: Embodiments of the present invention provide an LED lamp strip structure, a backlight module, a liquid crystal display device and a method of controlling the LED lamp strip structure. The LED lamp strip structure comprises: a circuit board; and at least a first LED sequence and a second LED sequence arranged in parallel on the circuit board, the first LED sequence having a plurality of predetermined intervals, and each LED in the second LED sequence corresponding to one of the plurality of predetermined intervals respectively.
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102.
公开(公告)号:US20180020550A1
公开(公告)日:2018-01-18
申请号:US15467004
申请日:2017-03-23
Applicant: Samsung Display Co., Ltd.
Inventor: Sehui JANG , Sung-dong PARK , Chongguk LEE , Byoungdoo JEONG
CPC classification number: H05K1/189 , H05K1/028 , H05K1/0298 , H05K1/111 , H05K1/117 , H05K1/118 , H05K1/144 , H05K1/147 , H05K2201/094 , H05K2201/09409 , H05K2201/09418 , H05K2201/10128
Abstract: A flexible film includes a base film including an edge portion which extends in a first direction, a plurality of wirings disposed on the base film, and a plurality of pads which is disposed in the edge portion of the base film and connected to the plurality of wirings. The plurality of pads disposed in the edge portion include a plurality of horizontal pads horizontally arranged in the first direction to define a pad row extended in the first direction; and a vertical pad including a plurality of vertically arranged pads arranged in a second direction perpendicular to the first direction, within a same pad row in which the plurality of horizontal pads are horizontally arranged.
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公开(公告)号:US20170359897A1
公开(公告)日:2017-12-14
申请号:US15620866
申请日:2017-06-13
Applicant: Infineon Technologies Austria AG
Inventor: Frank Pueschner , Peter Stampka , Jens Pohl , Marcus Janke
CPC classification number: H05K1/181 , G06K19/07722 , G06K19/07733 , G06K19/07737 , G06K19/07739 , G06K19/07741 , G06K19/07747 , G06K19/07766 , G06K19/07773 , H01R12/714 , H05K1/0275 , H05K1/11 , H05K1/113 , H05K3/4007 , H05K3/4608 , H05K3/4694 , H05K2201/086 , H05K2201/09409 , H05K2201/09445 , H05K2201/09663 , H05K2201/10098 , H05K2201/10719
Abstract: In various embodiments, a chip card module is provided. The chip card module includes a chip card module contact array having six contact pads that are arranged in two rows having three contact pads each in accordance with ISO 7816, and three additional contact pads that are arranged between the two rows. Each additional contact pad is electrically conductively connected to a respective associated contact pad from a row from the two rows.
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公开(公告)号:US09788426B2
公开(公告)日:2017-10-10
申请号:US15327476
申请日:2015-07-10
Applicant: FUJIKURA LTD. , DDK Ltd.
Inventor: Yuki Ishida , Masayuki Suzuki , Harunori Urai
CPC classification number: H05K1/115 , H01R12/77 , H01R12/78 , H01R12/88 , H05K1/111 , H05K1/113 , H05K1/117 , H05K1/144 , H05K2201/041 , H05K2201/09036 , H05K2201/09063 , H05K2201/09409
Abstract: A printed wiring board including: a first substrate on which a plurality of pads to be connected to a connector is arranged to form a front array and a rear array in two rows; a second substrate that is laminated on the first substrate and formed with first wirings connected to first pads of the front array and second wirings connected through vias to second pads of the rear array; engageable parts that are to be engaged with engagement parts of the connector; and one or more reinforcement layers that are provided at the frontward side in the connecting direction than the engageable parts of the first substrate and/or the second substrate. The wirings each have a part formed to have a constant width along the inserting direction to the connector and an expanded-width part expanded to have a wider width than the constant width in the inserting direction of the connector.
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公开(公告)号:US09774769B2
公开(公告)日:2017-09-26
申请号:US14869768
申请日:2015-09-29
Applicant: CANON KABUSHIKI KAISHA
Inventor: Takanori Suzuki , Koji Tsuduki , Hisatane Komori , Yasushi Kurihara
CPC classification number: H04N5/2253 , H05K1/111 , H05K1/117 , H05K3/3442 , H05K3/4697 , H05K2201/068 , H05K2201/09181 , H05K2201/094 , H05K2201/09409 , H05K2201/10151 , Y02P70/611
Abstract: A surface mounted electronic component is provided. The component includes a first and a second connection portion for performing connection to a mounting board. The first connection portion includes a joint region arranged on a lower surface. The second connection portion includes a lower surface region arranged on the lower surface, and a side surface region connected to the lower surface region and arranged on a side surface. In a direction along the side, the lower surface region is arranged apart from the joint region, a length of the lower surface region in the direction is longer than a length of the joint region, a length of the side surface region in the direction is shorter than the length of the lower surface region, and the side surface region is spaced apart from an end of the side surface.
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公开(公告)号:US20170202092A1
公开(公告)日:2017-07-13
申请号:US15326635
申请日:2014-08-12
Applicant: Advanced Bionics AG
Inventor: Lin Li , Jian Xie , Jeryle Walter
CPC classification number: H05K3/328 , A61N1/36036 , A61N1/3754 , H05K1/09 , H05K1/115 , H05K2201/09409 , H05K2201/09709 , H05K2201/1028 , H05K2201/10287 , H05K2201/10303 , H05K2201/10424 , H05K2201/10795 , H05K2201/10909 , H05K2201/10916 , H05K2203/0169 , H05K2203/0195 , Y10T29/49183
Abstract: Methods of connecting wires (126) to feedthrough pins (104) and apparatus including wires connected to feedthrough pins.
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公开(公告)号:US09620462B2
公开(公告)日:2017-04-11
申请号:US14048410
申请日:2013-10-08
Applicant: Maxim Integrated Products, Inc.
Inventor: Ruben C. Zeta , Edgardo L. Chua Ching Chua
CPC classification number: H01L23/576 , H01L23/49816 , H01L23/49838 , H01L25/105 , H01L25/50 , H01L2224/32145 , H01L2224/48091 , H01L2224/48227 , H01L2224/73265 , H01L2225/1023 , H01L2225/1058 , H01L2924/15311 , H01L2924/15321 , H01L2924/15331 , H01L2924/3025 , H05K1/0275 , H05K3/3436 , H05K2201/0379 , H05K2201/09409 , H05K2201/09681 , H01L2924/00014 , H01L2924/00
Abstract: A first cavity-down ball grid array (BGA) package includes a substrate member and an array of bond balls. The array of bond balls includes a pair of parallel extending rows of outer mesh bond balls and a row of inner signal bond balls that is parallel to the pair of rows of outer mesh bond balls. A surface-mount blocking element is disposed between the row of inner signal bond balls and the pair of rows of outer mesh bond balls. The surface-mount blocking element is either a passive or an active component of the BGA package. In one example, the first cavity-down BGA package is surface-mounted to a second cavity-down BGA package to form a package-on-package (POP) security module. The surface-mount blocking element provides additional physical barrier against the probing of the inner signal bond balls. Sensitive data is therefore protected from unauthorized access.
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公开(公告)号:US09516751B2
公开(公告)日:2016-12-06
申请号:US14417751
申请日:2013-05-17
Applicant: NGK SPARK PLUG CO., LTD.
Inventor: Takahiro Hayashi , Makoto Nagai , Seiji Mori , Tomohiro Nishida , Makoto Wakazono , Tatsuya Ito
CPC classification number: H05K1/111 , G03F7/038 , G03F7/20 , G03F7/2024 , G03F7/30 , H01L23/49822 , H01L2224/16237 , H05K1/0298 , H05K3/3436 , H05K3/3452 , H05K3/4644 , H05K2201/09409 , H05K2201/09427 , H05K2201/09709 , H05K2201/09845 , H05K2201/099 , H05K2201/10674 , H05K2203/058 , H05K2203/0594 , H05K2203/1476
Abstract: To provide a wiring board excellent in connection reliability with a semiconductor chip. A first buildup layer 31 where resin insulating layers 21 and 22 and a conductor layer 24 are laminated is formed at a substrate main surface 11 side of an organic wiring board 10. The conductor layer 24 for an outermost layer in the first buildup layer 31 includes a plurality of connecting terminal portions 41 for flip-chip mounting a semiconductor chip. The plurality of connecting terminal portions 41 is exposed through an opening portion 43 of a solder resist layer 25. Each connecting terminal portion 41 includes a connection region 51 for a semiconductor chip and a wiring region 52 disposed to extend from the connection region 51 along the planar direction. The solder resist layer 25 includes, within the opening portion 43, a side-surface covering portion 55 that covers the side surface of the connecting terminal portion 41 and a projecting wall portion 56 that is integrally formed with the side-surface covering portion 55 and disposed to project so as to intersect with the connection region 51.
Abstract translation: 提供与半导体芯片的连接可靠性优异的布线板。 在有机布线板10的基板主表面11侧形成有树脂绝缘层21,22和导体层24层叠的第一堆积层31.第一堆积层31中的最外层的导体层24包括 多个用于倒装芯片安装半导体芯片的连接端子部分41。 多个连接端子部分41通过阻焊层25的开口部分43露出。每个连接端子部分41包括用于半导体芯片的连接区域51和从连接区域51延伸的布线区域52 平面方向。 阻焊层25在开口部43内具有覆盖连接端子部41的侧面的侧面覆盖部55和与侧面覆盖部55一体形成的突出壁部56, 被设置为突出以与连接区域51相交。
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公开(公告)号:US09491851B2
公开(公告)日:2016-11-08
申请号:US14339470
申请日:2014-07-24
Applicant: WINTEK CORPORATION
Inventor: Jung-Sung Lin , Hsua-Yun Lee , Pin-Hao Chi , Chih-Yuan Lin , Ming-Chuan Lin
IPC: H02H9/00 , H05K1/02 , H05F3/00 , H05F3/02 , H01R13/648 , H01R12/71 , H01R12/70 , H01R12/77 , H05K1/11
CPC classification number: H05K1/0259 , H01R12/7005 , H01R12/714 , H01R12/775 , H01R13/6485 , H05F3/00 , H05F3/02 , H05K1/111 , H05K1/113 , H05K2201/09354 , H05K2201/09409 , H05K2201/09445 , H05K2201/097
Abstract: A connection structure of an electronic device includes a circuit board, a plurality of conductive contact pads and a conductive pattern. The conductive contact pads and the conductive pattern are disposed on the circuit board. The conductive contact pads are electrically insulated from one another. The conductive pattern is electrically insulated from the conductive contact pads. The conductive pattern is disposed on at least three sides of the conductive contact pads so as to generate an electrostatic discharge protection effect for the conductive contact pads.
Abstract translation: 电子设备的连接结构包括电路板,多个导电接触焊盘和导电图案。 导电接触焊盘和导电图案设置在电路板上。 导电接触垫彼此电绝缘。 导电图案与导电接触垫电绝缘。 导电图案设置在导电接触焊盘的至少三个侧面上,以便为导电接触焊盘产生静电放电保护效果。
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公开(公告)号:US20160286649A1
公开(公告)日:2016-09-29
申请号:US14929127
申请日:2015-10-30
Applicant: Samsung Display Co., Ltd.
Inventor: Dongwan CHOI
IPC: H05K1/14
CPC classification number: H05K1/147 , H05K1/0259 , H05K3/323 , H05K3/361 , H05K2201/09409 , H05K2201/10128
Abstract: A printed circuit board assembly includes: a first signal terminal row including a plurality of first signal terminals connected to a plurality of signal wirings of a flexible printed circuit board (FPCB), respectively; a first ground terminal row spaced from the first signal terminal row and including a plurality of first ground terminals connected to a plurality of ground wirings of the FPCB, respectively; a second signal terminal row including a plurality of second signal terminals connected to a plurality of signal wirings of a printed circuit board (PCB), respectively; and a second ground terminal row spaced from the second signal terminal row and including a plurality of second ground terminals connected to a plurality of ground wirings of the PCB, respectively. The first ground terminal row is closer to an end portion of the FPCB than the first signal terminal row.
Abstract translation: 印刷电路板组件包括:第一信号端子排,包括分别连接到柔性印刷电路板(FPCB)的多个信号布线的多个第一信号端子; 与第一信号端子排间隔开的第一接地端子列,分别包括连接到FPCB的多个接地布线的多个第一接地端子; 第二信号端子行,包括分别连接到印刷电路板(PCB)的多个信号布线的多个第二信号端子; 以及与第二信号端子排间隔开的第二接地端子列,并且分别包括连接到PCB的多个接地布线的多个第二接地端子。 第一接地端子排比第一信号端子排更靠近FPCB的端部。
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