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    Method and apparatus for clock uncertainty minimization
    111.
    发明授权
    Method and apparatus for clock uncertainty minimization 有权
    时钟不确定性最小化的方法和装置

    公开(公告)号：US06204712B1

    公开(公告)日：2001-03-20

    申请号：US09439077

    申请日：1999-11-12

    Applicant: Sergio D. Camerlo

    Inventor： Sergio D. Camerlo

    IPC: G06F104

    CPC classification number: H05K1/0233 ,  G06F1/10 ,  H05K1/0215 ,  H05K1/0231 ,  H05K2201/09336 ,  H05K2201/09345 ,  H05K2201/10689

    Abstract: A method and apparatus for drastically reducing timing uncertainties in clocked digital circuits simply, at virtually no cost, and using only standard clock drivers and simple, inexpensive electrical components is described. The method includes the steps of minimizing timing uncertainties by controlling both clock skew and clock jitter. Intrinsic clock skew is eliminated by ganging the outputs of a multi-line clock together onto a capacitive metal island disposed on a printed circuit board (PCB). Extrinsic clock skew is controlled through the use of wide, relatively high-capacitance traces of matched length and disposed on a single, common signal layer of the PCB, each leading to a respective receiver circuit and terminated identically. Clock jitter is controlled by electrically isolating a region of the PCB, disposing the clock driver in the region in such a way as to minimize noise, and providing quiet local power and ground to the region.

    Abstract translation: 描述了简单地实际上没有成本，并且仅使用标准时钟驱动器和简单，便宜的电气部件来大大降低时钟数字电路中的时序不确定性的方法和装置。 该方法包括通过控制时钟偏移和时钟抖动来最小化时序不确定性的步骤。 通过将多行时钟的输出结合在布置在印刷电路板（PCB）上的电容金属岛上来消除本征时钟偏移。 通过使用匹配长度的宽的相对较高电容的迹线来控制外部时钟偏移，并且布置在PCB的单个公共信号层上，每个通向相应的接收器电路并且相同地终止。 通过电气隔离PCB的区域来控制时钟抖动，将时钟驱动器设置在该区域中以使噪声最小化，并向该区域提供安静的局部电源和接地。

    Electronic signal time dealy device and method of making the same
    116.
    发明授权
    Electronic signal time dealy device and method of making the same 失效
    电子信号时间设备及其制作方法

    公开(公告)号：US4783359A

    公开(公告)日：1988-11-08

    申请号：US932180

    申请日：1986-11-18

    Applicant: Cathy A. Fleischer ,  Richard T. Traskos

    Inventor： Cathy A. Fleischer ,  Richard T. Traskos

    IPC: H01P9/00 ,  H05K1/00 ,  H05K1/02 ,  H05K3/38 ,  H05K3/46 ,  B32B3/00 ,  H02H5/04

    CPC classification number: H05K1/0248 ,  H01P9/00 ,  H05K1/024 ,  H05K3/4635 ,  H05K1/0393 ,  H05K2201/0129 ,  H05K2201/015 ,  H05K2201/0195 ,  H05K2201/051 ,  H05K2201/09263 ,  H05K2201/09336 ,  H05K3/386 ,  Y10S428/901 ,  Y10T428/24917 ,  Y10T428/3154

    Abstract: A preferably low dielectric constant polymeric bonding layer is applied or bonded (i.e., laminated or coated) to at least one side of a preferably low dielectric constant polymeric delay line substrate. Preferably, the melting or softening point of the bonding film is lower than the melting or softening point of the substrate so that the application (e.g. lamination) step is carried out at a temperature which is above the softening point of the bonding film, but below the softening point of the substrate (thereby insuring the integrity of the delay line circuit). Thereafter, the delay line/bonding layer assembly is rolled up and head sealed so as to melt the bonding layer, thus heat sealing the delay line package. As the package heats up (in, for example, a tightly fitting die), the materials expand and provide sufficient pressure to bond the circuit together.

    Abstract translation: 将优选低介电常数聚合物粘合层施加或结合（即，层压或涂覆）至优选低介电常数聚合物延迟线基材的至少一侧。 优选地，接合膜的熔融或软化点低于基材的熔化或软化点，使得涂覆（例如层压）步骤在高于粘合膜的软化点但低于 衬底的软化点（从而确保延迟线电路的完整性）。 此后，将延迟线/接合层组件卷起并头部密封以熔化接合层，从而热延伸线封装。 当包装加热（例如，紧密的模具）时，材料膨胀并提供足够的压力将电路结合在一起。

    Rolled delay line of the coplanar line type
    117.
    发明授权
    Rolled delay line of the coplanar line type 失效
    共面线类型的滚动延迟线

    公开(公告)号：US4675625A

    公开(公告)日：1987-06-23

    申请号：US760818

    申请日：1985-07-31

    Applicant: Joseph E. Johnston

    Inventor： Joseph E. Johnston

    IPC: H01P9/00 ,  H05K1/00 ,  H05K1/02

    CPC classification number: H05K1/0248 ,  H01P9/00 ,  H05K1/0393 ,  H05K2201/051 ,  H05K2201/0715 ,  H05K2201/09263 ,  H05K2201/09336

    Abstract: A time delay device for adjusting the arrival time of an electronic signal at a specific area in a circuit pattern is presented. The time delay device is comprised of a coplanar flexible circuit having a conductive pattern consisting of a signal line in a ground shield. The signal line is serpentine and makes one or more passes back and forth on the dielectric surface of the flexible circuit. The ground plane covers substantially the entire surface of the laminate except for a small gap on either side of the signal line. This circuit laminate is then tightly rolled up and permanently packaged in a suitable sheath or by encapsulation.

    Abstract translation: 提出了一种用于在电路图案中的特定区域调整电子信号的到达时间的延时装置。 时间延迟器件由具有由接地屏蔽中的信号线组成的导电图案的共面柔性电路构成。 信号线是蛇形的，并且使得一个或多个在柔性电路的电介质表面上前后传播。 接地平面覆盖了层叠体的整个表面，除了信号线两边的小间隙之外。 然后将该电路层压板紧密卷起并且永久包装在合适的护套中或通过封装。

    Aperture-coupled microwave apparatus
    118.
    发明授权
    Aperture-coupled microwave apparatus 失效
    光圈耦合微波装置

    公开(公告)号：US4571564A

    公开(公告)日：1986-02-18

    申请号：US532543

    申请日：1983-09-15

    Applicant: Maciej E. Znojkiewicz

    Inventor： Maciej E. Znojkiewicz

    IPC: H01P5/08 ,  H01P5/107 ,  H01P7/00 ,  H01P7/06 ,  H03B19/18 ,  H03D7/02 ,  H03D9/06 ,  H05K1/02 ,  H05K1/16 ,  H05K3/00 ,  H01P5/00 ,  H04B1/26

    CPC classification number: H05K1/0239 ,  H03D9/0641 ,  H03B19/18 ,  H05K1/0218 ,  H05K1/0272 ,  H05K1/162 ,  H05K2201/09054 ,  H05K2201/09236 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/10174 ,  H05K3/0061

    Abstract: In a microwave device, for example a microwave local oscillator with a harmonic mixer for feedback control, problems of coupling the mixer circuit to the R.F. cavity are overcome by providing a d.c. blocking capacitor of the mixer on a planar surface of a support extending across an aperture in one wall of the cavity. In preferred embodiments the capacitor is a planar device formed by a plurality of interdigitated fingers. These fingers are oriented to couple magnetically with the R.F. energy at the aperture in the cavity. The support conveniently comprises a printed circuit board having a ground plane on the same surface as the capacitor, which is located in a small opening in the ground plane. A second ground plane is provided on the opposite side of the printed circuit board, overlying the opening. The two ground planes are interconnected by plate-through-holes.

    Abstract translation: 在微波装置中，例如具有用于反馈控制的谐波混频器的微波本地振荡器，将混频器电路耦合到R.F.的问题。 通过提供直流电流来克服腔体。 混合器的阻塞电容器在穿过空腔的一个壁中的孔的支撑件的平坦表面上。 在优选实施例中，电容器是由多个叉指形成的平面器件。 这些指状物被定向成与R.F. 空腔孔径处的能量。 该支撑件方便地包括印刷电路板，该印刷电路板位于与接地平面中的小开口中的与电容器相同的表面上的接地平面。 第二接地平面设置在印刷电路板的相对侧上，覆盖开口。 两个接地平面通过板通孔相互连接。

    CIRCUIT BOARD AND ELECTRONIC-COMPONENT-EQUIPPED CIRCUIT BOARD
    119.
    发明公开
    CIRCUIT BOARD AND ELECTRONIC-COMPONENT-EQUIPPED CIRCUIT BOARD 审中-公开

    公开(公告)号：US20230380075A1

    公开(公告)日：2023-11-23

    申请号：US18229717

    申请日：2023-08-03

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Kenji MATSUDA

    IPC: H05K3/46 ,  H05K3/30 ,  H05K1/02 ,  H05K1/18

    CPC classification number: H05K3/4644 ,  H05K3/303 ,  H05K1/0242 ,  H05K1/181 ,  H05K2201/09336 ,  H05K2201/09354 ,  H05K2203/1572 ,  H05K2201/10098

    Abstract: A multilayer body includes insulator layers including a first insulator layer laminated in a vertical direction. Electrodes include a signal electrode and are provided at an upper main surface of the first insulator layer and arranged in a transverse direction. At least a portion of each of the electrodes is exposed to outside from a circuit board. First and second interlayer connection conductors extend through the first insulator layer in the vertical direction and electrically connect the signal electrode and a signal conductor layer. Mounting portions are located at the portions of the electrodes that are exposed to the outside from the circuit board. The first and second interlayer connection conductors are electrically connected to the signal electrode so as not to overlap the mounting portion that is provided at the signal electrode.

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