公开(公告)号：US09219461B2

公开(公告)日：2015-12-22

申请号：US14355900

申请日：2012-12-21

Applicant: Andrew LLC

Inventor： Martin Zimmerman

IPC: H01P5/02 ,  H03H7/00 ,  H01Q1/24 ,  H05K1/02 ,  H05K7/02 ,  H05K3/28 ,  H05K3/40

CPC classification number: H03H7/004 ,  H01L2924/0002 ,  H01P5/028 ,  H01Q1/246 ,  H05K1/0225 ,  H05K1/0239 ,  H05K3/28 ,  H05K3/40 ,  H05K2201/0175 ,  H05K2201/09309 ,  H05K2201/09336 ,  H05K2201/09618 ,  H05K2201/09872 ,  H01L2924/0001

Abstract: A blind-mate capacitive coupling interconnection between a main module enclosure one or more sub-module enclosures has coupling surfaces each with a ground portion and an aperture, an inner element provided in the aperture, spaced away from the ground portion. The coupling surfaces may be provided, for example, as traces on a printed circuit board. To accommodate a degree of mis-alignment, one of the inner elements may be provided larger than the other. Capacitive coupling between the coupling surfaces occurs when the coupling surfaces are mated together, retained in position, for example, by a mechanical fixture.

Abstract translation: 一个或多个子模块外壳之间的主模块外壳之间的盲配电容耦合互连具有各自具有接地部分和开口的耦合表面，设置在孔中的内部元件与接地部分间隔开。 耦合表面可以例如设置在印刷电路板上的迹线上。 为了适应一定程度的误配对，可以将内部元件中的一个设置得大于另一个。 耦合表面之间的电容耦合发生在耦合表面配合在一起时，例如通过机械夹具保持在适当的位置。

公开(公告)号：US20150353772A1

公开(公告)日：2015-12-10

申请号：US14760779

申请日：2014-01-10

Applicant: ALLNEX IP S.À.R.L.

Inventor： Abdullah EKIN ,  Michael J. DVORCHAK

IPC: C09D175/14 ,  B05D3/06

CPC classification number: C09D175/14 ,  B05D3/067 ,  C08G18/307 ,  C08G18/4277 ,  C08G18/672 ,  C08G18/725 ,  C08G18/7837 ,  C08G18/798 ,  C08G18/81 ,  C08G63/08 ,  C09D4/00 ,  C09D175/16 ,  H05K3/284 ,  H05K3/287 ,  H05K2201/09872

Abstract: Disclosed are one-component compositions that include: (1) an isocyanate-functional urethane acrylate and (2) a polyisocyanate containing allophanate and/or uretdione groups, wherein the one-component composition has a viscosity of less than or equal to about 800 mPa·s and an isocyanate content of greater than about 5% by weight, based on the weight of the one-component composition. Also disclosed are circuit boards and electronic components that are coated with such compositions.

Abstract translation: 公开了单组分组合物，其包括：（1）异氰酸酯官能的氨基甲酸酯丙烯酸酯和（2）含有脲基甲酸酯和/或脲二酮基团的多异氰酸酯，其中所述单组分组合物的粘度小于或等于约800mPa ·s和异氰酸酯含量大于约5重量％，基于单组分组合物的重量。 还公开了涂覆有这种组合物的电路板和电子部件。

公开(公告)号：US20150146399A1

公开(公告)日：2015-05-28

申请号：US14089744

申请日：2013-11-25

Applicant: LAKSHMINARAYAN VISWANATHAN ,  L.M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

Inventor： LAKSHMINARAYAN VISWANATHAN ,  L.M. Mahalingam ,  David F. Abdo ,  Jaynal A. Molla

IPC: H01L23/00 ,  B23K20/02 ,  B23K20/00 ,  B23K20/24 ,  B23K20/16 ,  B23K20/10 ,  H05K1/14 ,  B23K35/02

CPC classification number: H01L24/73 ,  B23K20/002 ,  B23K20/023 ,  B23K20/10 ,  B23K20/16 ,  B23K20/24 ,  B23K35/0244 ,  H01L23/3107 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/75 ,  H01L24/83 ,  H01L24/95 ,  H01L2224/05611 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/29139 ,  H01L2224/29144 ,  H01L2224/29147 ,  H01L2224/29155 ,  H01L2224/29164 ,  H01L2224/29339 ,  H01L2224/29344 ,  H01L2224/29347 ,  H01L2224/29355 ,  H01L2224/29364 ,  H01L2224/32225 ,  H01L2224/32238 ,  H01L2224/32245 ,  H01L2224/32258 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48137 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/75315 ,  H01L2224/75317 ,  H01L2224/83192 ,  H01L2224/83203 ,  H01L2224/83365 ,  H01L2224/83385 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83455 ,  H01L2224/8348 ,  H01L2224/83484 ,  H01L2224/8384 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01322 ,  H01L2924/04541 ,  H01L2924/04642 ,  H01L2924/0503 ,  H01L2924/1306 ,  H01L2924/15724 ,  H01L2924/15747 ,  H01L2924/15786 ,  H01L2924/15793 ,  H01L2924/181 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/2072 ,  H05K2203/1322 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/05599

Abstract: An embodiment of a method of attaching a semiconductor die to a substrate includes placing a bottom surface of the die over a top surface of the substrate with an intervening die attach material. The method further includes contacting a top surface of the semiconductor die and the top surface of the substrate with a conformal structure that includes a non-solid, pressure transmissive material, and applying a pressure to the conformal structure. The pressure is transmitted by the non-solid, pressure transmissive material to the top surface of the semiconductor die. The method further includes, while applying the pressure, exposing the assembly to a temperature that is sufficient to cause the die attach material to sinter. Before placing the die over the substrate, conductive mechanical lock features may be formed on the top surface of the substrate, and/or on the bottom surface of the semiconductor die.

Abstract translation: 将半导体管芯附接到衬底的方法的实施例包括使用插入的管芯附着材料将管芯的底表面放置在衬底的顶表面上。 该方法还包括使半导体管芯的顶表面和衬底的顶表面与保形结构接触，该保形结构包括非固体，压力传递材料，并向保形结构施加压力。 压力通过非固体的压力传递材料传递到半导体管芯的顶表面。 该方法还包括在施加压力的同时，将组件暴露于足以使管芯附着材料烧结的温度。 在将管芯置于衬底上之前，可以在衬底的顶表面和/或半导体管芯的底表面上形成导电的机械锁定特征。

公开(公告)号：US20150138740A1

公开(公告)日：2015-05-21

申请号：US14537250

申请日：2014-11-10

Applicant: SAMSUNG SDI CO., LTD.

Inventor： Kyungjae SHIN ,  Kiwoong KIM

IPC: C09D5/00 ,  H05K1/02 ,  H05K3/00 ,  H05K1/18

CPC classification number: C09D5/00 ,  C08J3/243 ,  C08K5/0025 ,  C08K2003/222 ,  C08K2003/2227 ,  C08K2003/2231 ,  C08K2003/2296 ,  C08K2003/282 ,  C08K2003/385 ,  C08L83/04 ,  H01L23/296 ,  H05K1/0259 ,  H05K1/18 ,  H05K3/0011 ,  H05K3/284 ,  H05K3/285 ,  H05K2201/0162 ,  H05K2201/09872 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10166 ,  H05K2201/10181

Abstract: An integrated silicone for protecting electronic devices includes a base resin, a thermal initiator, and a photoinitiator.

Abstract translation: 用于保护电子器件的集成硅氧烷包括基础树脂，热引发剂和光引发剂。

公开(公告)号：US20150092370A1

公开(公告)日：2015-04-02

申请号：US14566043

申请日：2014-12-10

Applicant: HZO, Inc.

Inventor： David James Astle ,  Tyler Christensen Child ,  Vimal Kumar Kasagani ,  Cameron LaMar Loose ,  Blake LeRoy Stevens ,  Max Ernest Sorenson

IPC: H05K1/18 ,  H01L21/67

CPC classification number: B05D1/322 ,  C09J9/00 ,  C09J2201/61 ,  H01L21/56 ,  H01L21/561 ,  H01L21/67011 ,  H01L21/6715 ,  H01L23/3121 ,  H01L2924/0002 ,  H05K1/181 ,  H05K3/0073 ,  H05K3/0079 ,  H05K3/284 ,  H05K2201/0145 ,  H05K2201/09872 ,  H01L2924/00

Abstract: A method for applying a protective coating to selected portions of a substrate is disclosed. The method includes applying a mask to or forming a mask on at least one portion of the substrate that is not to be covered with the protective coating. The mask may be selectively formed by applying a flowable material to the substrate. Alternatively, the mask may be formed from a preformed film. With the mask in place, the protective coating may be applied to the substrate and the mask. A portion of the protective coating that overlies the mask may be delineated from other portions of the protective coating; for example, by cutting, weakening or removing material from the protective coating at locations at or adjacent to the perimeter of the mask. The portion of the protective coating that overlies the mask, and the mask, may then be removed from the substrate.

Abstract translation: 公开了一种将保护涂层施加到衬底的选定部分的方法。 该方法包括在不被保护涂层覆盖的基底的至少一部分上施加掩模或形成掩模。 可以通过将可流动材料施加到基底来选择性地形成掩模。 或者，掩模可以由预成型膜形成。 在掩模就位的情况下，可以将保护涂层施加到基底和掩模上。 覆盖在掩模上的保护涂层的一部分可以从保护涂层的其它部分描绘出来; 例如，通过在掩模的周边或附近的位置处切割，削弱或从保护涂层去除材料。 然后可以将覆盖在掩模上的保护涂层和掩模的部分从基材上除去。

公开(公告)号：US20140342113A1

公开(公告)日：2014-11-20

申请号：US14221833

申请日：2014-03-21

Applicant: United States of America as represented by the Secretary of the Navy

Inventor： Nishkamraj U. Deshpande ,  H. Fred Barsun ,  Ron Shoultz

IPC: H05K1/02 ,  H05K3/30

CPC classification number: H05K1/0275 ,  H05K3/28 ,  H05K2201/0251 ,  H05K2201/026 ,  H05K2201/0769 ,  H05K2201/09872 ,  H05K2203/161 ,  Y10T29/49146 ,  Y10T428/1405

Abstract: A method and an apparatus for mitigating electrical failures caused by intrusive structures. Such structures can be tin whiskers forming on electrical circuits. In an illustrative embodiment, nano-capsules are filled with some type of insulative and adhesive fluid that is adapted to bind to and coat an intrusive structure, e.g., a whisker, making the whisker electrically inactive and thereby reducing the electrical faults that can be caused by the whisker. In another illustrative embodiment, randomly oriented nano-fibers having an elastic modulus higher than tin or any other whisker material is used to arrest a growth or movement of a whisker and further reduce a likelihood that a whisker can cause an electrical fault.

Abstract translation: 一种用于减轻由侵入式结构引起的电气故障的方法和装置。 这种结构可以是在电路上形成的锡晶须。 在说明性实施例中，纳米胶囊填充有某种类型的绝缘和粘合剂流体，其适于结合并涂覆侵入结构（例如晶须），使晶须电不活动，从而减少可能引起的电气故障 由晶须 在另一个说明性实施例中，使用弹性模量高于锡或任何其它晶须材料的随机取向的纳米纤维来阻止晶须的生长或移动，并进一步降低晶须可能导致电气故障的可能性。

公开(公告)号：US20140264423A1

公开(公告)日：2014-09-18

申请号：US13948512

申请日：2013-07-23

Applicant: Grote Industries, LLC

Inventor： Timothy Webster Brooks ,  Scott J. Jones ,  Martin J. Marx ,  Cesar Perez-Bolivar ,  James E. Roberts

IPC: H01L33/56

CPC classification number: H01L33/56 ,  F21S4/22 ,  F21Y2103/10 ,  F21Y2115/10 ,  H01L25/0753 ,  H01L33/64 ,  H01L33/644 ,  H01L2924/0002 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2201/10106 ,  H05K2201/10977 ,  H01L2924/00

Abstract: A lighting element is provided, comprising: a substrate; first and second conductive elements located on the substrate; a light-emitting element having first and second contacts that are both on a first surface of the light-emitting element, the light-emitting element emitting light from a second surface opposite the first surface; a first conductive connector located between the first conductive element and the first contact, electrically connecting the first conductive element to the first contact; a second conductive connector located between the second conductive element and the second contact, to electrically connecting the second conductive element to the second contact; a first protective conformal coating located adjacent to the second surface; and an affixing layer located between the flexible substrate and the first protective conformal coating, the affixing layer affixing the first protective conformal coating to the flexible substrate, wherein the first protective conformal coating is substantially transparent to light.

Abstract translation: 提供了一种照明元件，包括：基板; 位于基板上的第一和第二导电元件; 所述发光元件具有在所述发光元件的第一表面上的第一和第二触点，所述发光元件从与所述第一表面相对的第二表面发射光; 位于所述第一导电元件和所述第一触点之间的第一导电连接器，将所述第一导电元件电连接到所述第一触点; 位于所述第二导电元件和所述第二触点之间的第二导电连接器，用于将所述第二导电元件电连接到所述第二触点; 位于第二表面附近的第一保护性保形涂层; 以及位于所述柔性基板和所述第一保护性保形涂层之间的固定层，所述固定层将所述第一保护性保形涂层固定到所述柔性基板，其中所述第一保护性保形涂层对于光基本上是透明的。

公开(公告)号：US20140254101A1

公开(公告)日：2014-09-11

申请号：US13786358

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Mark A. CARTER ,  Yang ZHANG ,  Yongsheng PENG ,  Jack B. STEENSTRA ,  Michael G. BARRETT

IPC: H05K7/20 ,  H05K9/00 ,  H05K3/30

CPC classification number: H05K7/205 ,  H01L23/3121 ,  H01L23/3677 ,  H01L23/5389 ,  H01L23/552 ,  H01L2924/0002 ,  H01L2924/19105 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/0218 ,  H05K1/141 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/284 ,  H05K3/30 ,  H05K3/4608 ,  H05K9/00 ,  H05K2201/068 ,  H05K2201/09872 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2924/00

Abstract: Method and apparatuses for making a smart phone on a chip (SPOC) are described. Active components may be embedded into a copper core. In an aspect, and optionally, passive components may also be embedded into the copper core. Printed circuit board (PCB) laminate may be layered above and below the copper core. A copper ground plane may be fixed underneath the layer of PCB laminate below, and furthest from, the copper core. One or more additional components may be surface mounted on top of the PCB laminate layers above the copper core. A conformal coating may be applied to completely and thinly encase the one or more surface mounted additional components. The conformal coating may include trenching and a copper sputter coating finish.

Abstract translation: 描述用于制造芯片上的智能手机（SPOC）的方法和装置。 活性组分可嵌入铜芯中。 在一方面，并​​且可选地，无源部件也可以嵌入到铜芯中。 印刷电路板（PCB）层压板可以在铜芯上方和下方分层。 铜接地平面可以固定在PCB层压体下方，最远离铜芯的位置。 一个或多个附加部件可以表面安装在铜芯上方的PCB层叠层的顶部上。 可以施加保形涂层以完全和薄地包住一个或多个表面安装的附加部件。 保形涂层可以包括开沟和铜溅射涂层。

公开(公告)号：US08748754B2

公开(公告)日：2014-06-10

申请号：US13301941

申请日：2011-11-22

Applicant: Christopher James Kapusta ,  Donald Paul Cunningham

Inventor： Christopher James Kapusta ,  Donald Paul Cunningham

IPC: H05K9/00

CPC classification number: H05K1/0218 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/20 ,  H01L2224/24195 ,  H01L2224/73267 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/284 ,  H05K2201/0715 ,  H05K2201/09872 ,  H05K2201/10515 ,  H05K2201/1053 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49155

Abstract: A system and method of forming a patterned conformal structure for an electrical system is disclosed. The conformal structure includes a dielectric coating shaped to conform to a surface of an electrical system, with the dielectric coating having a plurality of openings therein positioned over contact pads on the surface of the electrical system. The conformal structure also includes a patterned conductive coating layered on the dielectric coating and on the contact pads such that an electrical connection is formed between the patterned conductive coating and the contact pads. The patterned conductive coating comprises at least one of an interconnect system, a shielding structure, and a thermal path.

Abstract translation: 公开了一种形成用于电气系统的图案化保形结构的系统和方法。 共形结​​构包括形成为符合电气系统的表面的电介质涂层，其中电介质涂层具有位于电气系统表面上的接触焊盘上的多个开口。 共形结​​构还包括层叠在电介质涂层上和接触焊盘上的图案化导电涂层，使得在图案化的导电涂层和接触焊盘之间形成电连接。 图案化导电涂层包括互连系统，屏蔽结构和热路径中的至少一个。

公开(公告)号：US20130240256A1

公开(公告)日：2013-09-19

申请号：US13885119

申请日：2011-11-09

Applicant: Timothy Von Werne

Inventor： Timothy Von Werne

IPC: H05K3/28 ,  H05K1/09 ,  H05K1/03

CPC classification number: H05K3/282 ,  H05K1/032 ,  H05K1/09 ,  H05K3/284 ,  H05K2201/015 ,  H05K2201/0179 ,  H05K2201/09872 ,  H05K2203/095

Abstract: A method for reducing creep corrosion on a printed circuit board, the printed circuit board comprising a substrate, a plurality of electrically conductive tracks located on at least one surface of the substrate, a solder mask coating at least a first area of the plurality of electrically conductive tracks and a surface finish coating at least a second area of the plurality of electrically conductive tracks, the method comprising depositing by plasma-polymerization a fluorohydrocarbon onto at least part of the solder mask and at least part of the surface finish.

Abstract translation: 一种用于减少印刷电路板上的蠕变腐蚀的方法，所述印刷电路板包括基板，位于所述基板的至少一个表面上的多个导电轨道，焊接掩模涂覆所述多个电气的至少第一区域 导电轨道和表面光洁度涂层，所述方法包括通过将氟代烃等离子体聚合到至少部分焊料掩模和至少部分表面光洁度上进行沉积。