METHODS FOR LIQUID TRANSER COATING OF THREE-DIMENSIONAL SUBSTRATES
    131.
    发明申请
    METHODS FOR LIQUID TRANSER COATING OF THREE-DIMENSIONAL SUBSTRATES 有权
    三维基质液体交联涂层方法

    公开(公告)号:US20140127834A1

    公开(公告)日:2014-05-08

    申请号:US13942150

    申请日:2013-07-15

    Applicant: Solexel, Inc.

    Abstract: Methods here disclosed provide for selectively coating the top surfaces or ridges of a 3-D substrate while avoiding liquid coating material wicking into micro cavities on 3-D substrates. The substrate includes holes formed in a three-dimensional substrate by forming a sacrificial layer on a template. The template includes a template substrate with posts and trenches between the posts. The steps include subsequently depositing a semiconductor layer and selectively etching the sacrificial layer. Then, the steps include releasing the semiconductor layer from the template and coating the 3-D substrate using a liquid transfer coating step for applying a liquid coating material to a surface of the 3-D substrate. The method may further include coating the 3-D substrate by selectively coating the top ridges or surfaces of the substrate.

    Abstract translation: 这里公开的方法提供了选择性地涂覆3-D衬底的顶表面或脊,同时避免液体涂覆材料吸收到3-D衬底上的微腔中。 衬底包括通过在模板上形成牺牲层而形成在三维衬底中的孔。 模板包括具有在柱之间的柱和沟槽的模板衬底。 这些步骤包括随后沉积半导体层并选择性地蚀刻牺牲层。 然后,该步骤包括从模板中释放半导体层并使用用于将液体涂覆材料施加到3-D衬底的表面的液体转移涂覆步骤涂覆3-D衬底。 该方法还可以包括通过选择性地涂覆衬底的顶部脊或表面来涂覆3-D衬底。

    Fixing metal bracket for component mounted on circuit board
    132.
    发明授权
    Fixing metal bracket for component mounted on circuit board 失效
    固定金属支架,用于安装在电路板上的组件

    公开(公告)号:US08659911B2

    公开(公告)日:2014-02-25

    申请号:US13811830

    申请日:2011-07-21

    Applicant: Takashi Muro

    Inventor: Takashi Muro

    Abstract: A fixing metal bracket for a component mounted on a circuit board, includes a solder bonding plate section to be solder-fixed on a surface of a circuit board with a cream solder, and a component fixing section to be fixed to a component mounted on the circuit board. An annular through-groove is formed on the solder bonding plate section at a position surrounding a central area thereof. An island-shaped portion at the inside of the through-groove is separated from a peripheral portion at the outside of the through-groove while the connection part is remained. A step is formed on a solder bonding face of the connection part. Pure Sn plating is applied to the solder bonding face of the island-shaped portion and whisker resistance plating is applied to a surface of a portion other than the island-shaped portion.

    Abstract translation: 一种用于安装在电路板上的部件的固定金属支架,包括用焊膏固定在具有膏状焊料的电路板表面上的焊接接合板部分和固定到安装在该焊盘上的部件的部件固定部分 电路板。 在焊接接合板部分周围围绕其中心区域的位置处形成环形通槽。 在通孔的内侧的岛状部分与通孔的外侧的周边部分分离,同时保持连接部分。 在连接部的焊接面上形成台阶。 将纯锡电镀施加到岛状部分的焊料接合面上,并且将耐晶须电镀施加到岛状部以外的部分的表面。

    Method of manufacturing a stacked foil sheet device
    133.
    发明授权
    Method of manufacturing a stacked foil sheet device 失效
    层叠箔片装置的制造方法

    公开(公告)号:US08640332B2

    公开(公告)日:2014-02-04

    申请号:US12823946

    申请日:2010-06-25

    Abstract: The invention relates to a method of aligning a flexible foil sheet having a general first foil sheet length direction to form stacked foil sheet layers on a reel having a reel diameter. The method comprises providing multiple alignment markers in the foil sheet, distanced conform the reel diameter and each having an mark length direction transverse to the first foil sheet length direction, to form protrusions and corresponding recesses on opposite faces of the foil sheet; winding the foil sheet on the reel in the first foil sheet length direction of the foil sheet; and co-aligning the alignment markers to have protrusions of one mark matching with a recess of another mark, so as to block relative movement of the stacked foil sheet layers in the first foil sheet length direction. Preferably, the foil sheet layers are provided with device functionality to form a stacked foil sheet layered device.

    Abstract translation: 本发明涉及一种对准具有一般第一箔片长度方向的柔性箔片的方法,以在具有卷轴直径的卷轴上形成叠层的箔片层。 该方法包括在箔片中设置多个对准标记,远离卷轴直径,并且每个具有横向于第一箔片长度方向的标记长度方向,以在箔片的相对面上形成突起和相应的凹槽; 在箔片的第一箔片长度方向上将箔片卷绕在卷轴上; 并且使对准标记共同对准具有与另一标记的凹部匹配的一个标记的突起,以阻止层叠的箔片层在第一箔片长度方向上的相对移动。 优选地,箔片层具有器件功能以形成层叠的箔片层状器件。

    STACKED FOIL SHEET DEVICE
    134.
    发明申请
    STACKED FOIL SHEET DEVICE 失效
    堆叠式盖片装置

    公开(公告)号:US20130306227A9

    公开(公告)日:2013-11-21

    申请号:US12823946

    申请日:2010-06-25

    Abstract: The invention relates to a method of aligning a flexible foil sheet having a general first foil sheet length direction to form stacked foil sheet layers on a reel having a reel diameter. The method comprises providing multiple alignment markers in the foil sheet. distanced conform the reel diameter and each having an mark length direction transverse to the first foil sheet length direction, to form protrusions and corresponding recesses on opposite faces of the foil sheet; winding the foil sheet on the reel in the first foil sheet length direction of the foil sheet; and co-aligning the alignment markers to have protrusions of one mark matching with a recess of another mark, so as to block relative movement of the stacked foil sheet layers in the first foil sheet length direction. Preferably, the foil sheet layers are provided with device functionality to form a stacked foil sheet layered device.

    Abstract translation: 本发明涉及一种对准具有一般第一箔片长度方向的柔性箔片的方法,以在具有卷轴直径的卷轴上形成叠层的箔片层。 该方法包括在箔片中提供多个对准标记。 间距适应卷轴直径并且每个具有横向于第一箔片长度方向的标记长度方向,以在箔片的相对面上形成突起和相应的凹槽; 在箔片的第一箔片长度方向上将箔片卷绕在卷轴上; 并且使对准标记共同对准具有与另一标记的凹部匹配的一个标记的突起,以阻止层叠的箔片层在第一箔片长度方向上的相对移动。 优选地,箔片层具有器件功能以形成层叠的箔片层状器件。

    ELECTRIC CIRCUIT CONFIGURATION HAVING AN MID CIRCUIT CARRIER AND A CONNECTING INTERFACE CONNECTED TO IT
    137.
    发明申请
    ELECTRIC CIRCUIT CONFIGURATION HAVING AN MID CIRCUIT CARRIER AND A CONNECTING INTERFACE CONNECTED TO IT 有权
    具有中间电路承载器的电气电路配置和连接到它的连接接口

    公开(公告)号:US20110083894A1

    公开(公告)日:2011-04-14

    申请号:US12674129

    申请日:2008-07-18

    Applicant: Stefan Kopf

    Inventor: Stefan Kopf

    Abstract: An electric circuit configuration having an MID circuit carrier and a connecting interface, the connecting interface being situated on a surface of the MID circuit carrier. The electric circuit configuration further includes at least one electrical contact pair having at least one connecting interface contact element and at least one MID contact element that is provided on the surface and is situated on the connecting interface contact element. The exemplary embodiments and/or exemplary methods of the present invention further relates to a contact element group having at least one electrical contact element for the electrical contacting of an MID circuit carrier, which is developed on a surface of an MID circuit carrier, is electrically connected to it, and extends away from the surface. The at least one contact element is connected to a line element of the MID circuit carrier.

    Abstract translation: 一种具有MID电路载体和连接接口的电路结构,该连接接口位于MID电路载体的表面上。 电路结构还包括至少一个电接触对,其具有至少一个连接接口接触元件和设置在表面上并位于连接接口接触元件上的至少一个MID接触元件。 本发明的示例性实施例和/或示例性方法还涉及一种接触元件组,其具有至少一个电接触元件,用于在MID电路载体的表面上显影的MID电路载体的电接触, 连接到它,并远离表面延伸。 所述至少一个接触元件连接到所述MID电路载体的线路元件。

    Semiconductor package having connecting bumps
    139.
    发明授权
    Semiconductor package having connecting bumps 有权
    具有连接凸块的半导体封装

    公开(公告)号:US07838982B2

    公开(公告)日:2010-11-23

    申请号:US11304868

    申请日:2005-12-14

    Inventor: Junichi Nakamura

    Abstract: A semiconductor package and a fabrication method thereof are disclosed, whereby an environmental problem is solved by using external connection terminals or semiconductor element-mounting terminals containing a smaller amount of lead, while at the same time achieving a fine pitch of the terminals. The semiconductor package includes a board (20) including a plurality of insulating resin layers, semiconductor element-mounting terminals (18) formed on the uppermost surface of the board, and external connection terminals (12) formed on the bottom surface thereof. Each external connection terminal (12) is formed as a bump projected downward from the bottom surface of the package, and each bump is filled with the insulating resin (14) while the surface thereof is covered by a metal (16). Wiring (24), (26) including a conductor via (26a) electrically connect the metal of the metal layer 16 and the semiconductor element-mounting terminals (18).

    Abstract translation: 公开了一种半导体封装及其制造方法,通过使用包含较少量的引线的外部连接端子或半导体元件安装端子,同时实现端子的精细间距来解决环境问题。 半导体封装包括:多个绝缘树脂层的基板(20),形成在基板的最上表面上的半导体元件安装端子(18)和形成在其底面上的外部连接端子(12)。 每个外部连接端子(12)形成为从封装的底表面向下突出的凸起,并且每个凸起都填充有绝缘树脂(14),同时其表面被金属(16)覆盖。 包括导体通孔(26a)的布线(24),(26)将金属层16的金属与半导体元件安装端子(18)电连接。

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