公开(公告)号：US20180359864A1

公开(公告)日：2018-12-13

申请号：US16003474

申请日：2018-06-08

Applicant: PITYU CONTROLS INC.

Inventor： Stevan DOBI

IPC: H05K3/34 ,  H05K1/18 ,  B23K1/00

CPC classification number: H05K3/3442 ,  B23K1/0016 ,  B23K2101/42 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/09427 ,  H05K2201/10022 ,  H05K2201/10174 ,  H05K2201/10583 ,  H05K2203/048

Abstract: A cradle for a metal electrode leadless face (MELF) device is provided. The cradle can include at least one pad, such as a solder pad, to be connected to a printed circuit board (PCB) or similar board. The pad can be configured to receive a MELF device. Such a configuration can improve positioning and alignment of the MELF device and prevent or reduce movement of the MELF device prior to or during soldering. The pad can include boundaries to engage the MELF device for alignment and to prevent or reduce movement. The boundaries of the pad can include inlets, extensions, troughs, borders, and/or other features to engage the MELF device. Boards including such cradles are also provided. Further, methods of installing a MELF device on a board using a cradle are also provided.

公开(公告)号：US10038264B2

公开(公告)日：2018-07-31

申请号：US15351237

申请日：2016-11-14

Applicant: Microsoft Technology Licensing, LLC

Inventor： David Lukofsky ,  Joseph Christopher Bolling ,  Jeffrey M. Quackenbush ,  Tapani von Rauner

IPC: H01R12/00 ,  H01R12/91 ,  H01R12/78 ,  H01R12/72 ,  H04N13/04

CPC classification number: H01R12/91 ,  H01R12/721 ,  H01R12/78 ,  H04N13/344 ,  H04N2213/001 ,  H04N2213/008 ,  H05K1/0221 ,  H05K1/0295 ,  H05K1/11 ,  H05K3/361 ,  H05K2201/09272 ,  H05K2201/09381 ,  H05K2201/0939

Abstract: A universal coupling is disclosed for electrically and mechanically connecting flexible printed circuit (FPC) components within asymmetric FPC modules. The universal coupling allows a first FPC component to be connected to a second FPC component in two or more different orientations. This allows identical FPC components to be used in two or more asymmetric FPC modules. This in turn allows a reduction in the number of parts and tooling required to fabricate the two or more asymmetric FPC modules, and a simplification of the fabrication process.

公开(公告)号：US09883589B2

公开(公告)日：2018-01-30

申请号：US14764795

申请日：2014-07-30

Applicant: KYOCERA Corporation

Inventor： Kouichi Kawasaki

IPC: H05K7/10 ,  H05K1/11 ,  H01L23/13 ,  H01L23/498 ,  H01L23/24 ,  H01L23/00 ,  H05K3/34 ,  H05K1/18 ,  H05K1/02 ,  H01R9/00 ,  H01L23/48 ,  H05K3/24 ,  H05K3/46

CPC classification number: H05K1/111 ,  H01L23/13 ,  H01L23/24 ,  H01L23/49838 ,  H01L24/32 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/73265 ,  H01L2224/83385 ,  H01L2924/181 ,  H05K1/0209 ,  H05K1/181 ,  H05K3/243 ,  H05K3/244 ,  H05K3/3431 ,  H05K3/4629 ,  H05K2201/09154 ,  H05K2201/09163 ,  H05K2201/09381 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09663 ,  H05K2201/097 ,  H05K2201/098 ,  H05K2201/10068 ,  H05K2201/10075 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2201/2054 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: A wiring board has an insulation base plate, and a plurality of electrodes provided adjacent to each other in plan view on the insulation base plate, the electrodes have an opening in the outer periphery and a slit oriented from the outer periphery to the interior, and, among two electrodes adjacent to each other, the slit in one electrode has a central line intersecting the outer periphery of the other electrode.

公开(公告)号：US09872388B2

公开(公告)日：2018-01-16

申请号：US14630048

申请日：2015-02-24

Applicant: FANUC Corporation

Inventor： Nobuhisa Sugimoto ,  Takeshi Sawada

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K1/181 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/09381 ,  Y02P70/611

Abstract: In a printed wiring board on which an electronic component comprising electrode terminal rows on four peripheral sides or two opposite sides thereof is mounted, each of pads at the both ends of pad rows corresponding to the electrode terminal rows extend outwardly relative to the other pads in the direction of arrangement of the pads and has a shape obtained by diagonally cutting a corner located farthest from the center of the electronic component.

公开(公告)号：US20170064831A1

公开(公告)日：2017-03-02

申请号：US15247970

申请日：2016-08-26

Applicant: Oclaro Japan, Inc.

Inventor： Daisuke NOGUCHI ,  Hiroshi YAMAMOTO

IPC: H05K1/18 ,  H05K1/02 ,  H01S5/022 ,  H05K1/14

CPC classification number: H05K1/117 ,  G02B6/4279 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/141 ,  H05K2201/09381 ,  H05K2201/10121 ,  H05K2201/1034 ,  H05K2203/049

Abstract: The second wiring pattern includes extended regions from the main body side to the projecting portions as seen in a direction in which the pair of leads extend, and wiring regions continuously spreading from the extended regions in a direction away from the main body. Supposing that a length of the wiring region from an end of the projecting portion as a reference point to a farthest position in a direction away from the main body is a first width and a width of the extended region in a direction parallel to a side opposed to the main body side through the end of the projecting portion is a second width, the first width is smaller than the second width. The second insulating substrate is sandwiched between the second wiring pattern and a base, and thereby, a capacitance is formed.

Abstract translation: 第二布线图案包括从一对引线延伸的方向看，从主体侧到突出部分的延伸区域，以及布线区域沿远离主体的方向从延伸区域连续扩展。 假设从作为基准点的突出部分的端部到远离主体的方向上的最远位置的布线区域的长度是与平行于主体的一侧的方向上的延伸区域的第一宽度和宽度 通过突出部分的端部到主体侧是第二宽度，第一宽度小于第二宽度。 第二绝缘基板被夹在第二布线图案和基底之间，从而形成电容。

公开(公告)号：US20170059647A1

公开(公告)日：2017-03-02

申请号：US14838605

申请日：2015-08-28

Applicant: Oracle International Corporation

Inventor： Stephanie Moran ,  Michael C. Freda ,  Karl Sauter

IPC: G01R31/28 ,  H05K1/02 ,  H05K1/11

CPC classification number: G01R31/2813 ,  H05K1/0266 ,  H05K1/0268 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/167 ,  H05K3/0052 ,  H05K3/0097 ,  H05K3/4679 ,  H05K2201/09381 ,  H05K2201/09636 ,  H05K2201/097 ,  H05K2201/09781 ,  H05K2203/166

Abstract: A method and apparatus for determining misregistration of internal layers of a PCB using resistance measurements is disclosed. In one embodiment, a method includes measuring a first resistance between a first center terminal and a first peripheral terminal of a first registration coupon on a printed circuit board (PCB) panel including at least one PCB. The method further includes measuring a second resistance between the first center terminal and a second peripheral terminal of the first registration coupon, wherein the first and second peripheral terminals are associated with a first internal layer of the PCB.A difference between the first and second resistances is then calculated. Then, based on this difference, a determination is made of a distance of misregistration of the first internal layer, if any, along a first axis.

Abstract translation: 然后计算第一和第二电阻之间的差。 然后，基于该差异，确定沿着第一轴线的第一内层的配准距离（如果有的话）。

公开(公告)号：US09583463B2

公开(公告)日：2017-02-28

申请号：US14727885

申请日：2015-06-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seon-Sik Kim ,  Changwoo Koo ,  Wooseop Kim ,  Jungjoon Lee ,  Dongmin Jang

IPC: H05K7/10 ,  H05K7/12 ,  H01L25/065 ,  H05K1/11 ,  H05K3/34

CPC classification number: H01L25/0655 ,  H01L25/16 ,  H01L2924/0002 ,  H05K1/111 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/10022 ,  H05K2201/10159 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2924/00

Abstract: A semiconductor module includes: a module board, a plurality of chips mounted on the module board, and a plurality of array resistors mounted on the module board, the plurality of array resistors including at least a first array resistor. The first array resistor may include a substrate comprising a top surface, a bottom surface opposite the top surface, and first to fourth side surfaces connecting the top surface to the bottom surface, the first and third side surfaces being opposite each other, and the second and fourth side surfaces being opposite each other; a plurality of first electrodes disposed on the first side surface of the substrate, each first electrode including at least a first portion on the first side surface of the substrate and a second portion on the bottom surface of the substrate; a plurality of second electrodes disposed on the third side surface of the substrate, each second electrode opposite a respective first electrode and including at least a first portion on the third side surface of the substrate and a second portion on the bottom surface of the substrate; for each pair of respective first and second electrodes opposite each other, a resistor disposed on the substrate between the respective first and second electrodes; and at least one third electrode disposed on the second side surface of the substrate, the third electrode including at least a first portion on the second side surface of the substrate and a second portion on the bottom surface of the substrate. Each of the first electrodes, the second electrodes, and the third electrode may be bonded to the module board.

Abstract translation: 半导体模块包括：模块板，安装在模块板上的多个芯片，以及安装在模块板上的多个阵列电阻器，所述多个阵列电阻器至少包括第一阵列电阻器。 第一阵列电阻器可以包括基板，其包括顶表面，与顶表面相对的底表面，以及将顶表面连接到底表面的第一至第四侧表面，第一和第三侧表面彼此相对，第二 和第四侧面彼此相对; 多个第一电极，设置在所述基板的第一侧表面上，每个第一电极至少包括在所述基板的第一侧表面上的第一部分和所述基板的底表面上的第二部分; 多个第二电极，设置在所述基板的第三侧表面上，每个第二电极与相应的第一电极相对，并且至少包括在所述基板的第三侧表面上的第一部分和所述基板的底表面上的第二部分; 对于彼此相对的每对相应的第一和第二电极，设置在相应的第一和第二电极之间的基板上的电阻器; 以及设置在所述基板的所述第二侧表面上的至少一个第三电极，所述第三电极至少包括所述基板的第二侧表面上的第一部分和所述基板的底表面上的第二部分。 第一电极，第二电极和第三电极中的每一个可以结合到模块板。

公开(公告)号：US09565775B2

公开(公告)日：2017-02-07

申请号：US14469782

申请日：2014-08-27

Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.

Inventor： Noriyoshi Shimizu ,  Wataru Kaneda ,  Hiromu Arisaka ,  Akio Rokugawa

IPC: H05K1/11 ,  H05K3/42 ,  H05K1/00 ,  H05K1/18 ,  H05K7/10 ,  H05K3/38 ,  H05K3/46

CPC classification number: H05K3/421 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H05K1/115 ,  H05K1/116 ,  H05K3/38 ,  H05K3/4644 ,  H05K2201/0338 ,  H05K2201/0352 ,  H05K2201/09381 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/096 ,  H05K2201/0979 ,  H05K2201/09827 ,  H05K2201/09854 ,  H05K2201/2072 ,  H05K2203/0789 ,  H01L2924/00

Abstract: A wiring board includes a first insulating layer coating a first wiring layer. A first through hole is opened in a surface of the first insulating layer and exposes a surface of the first wiring layer. A first via arranged in the first through hole includes an end surface exposed to the surface of the first insulating layer. A gap is formed between the first insulating layer and the first via in the first through hole. A second wiring layer is stacked on the surface of the first insulating layer and the end surface of the first via. The second wiring layer includes a pad filling the gap. The pad is greater in planar shape than the first through hole.

Abstract translation: 布线板包括涂覆第一布线层的第一绝缘层。 第一通孔在第一绝缘层的表面上开放，并露出第一布线层的表面。 布置在第一通孔中的第一通孔包括暴露于第一绝缘层的表面的端表面。 在第一通孔中的第一绝缘层和第一通孔之间形成间隙。 在第一绝缘层的表面和第一通孔的端面上堆叠第二布线层。 第二布线层包括填充间隙的垫。 该垫的平面形状大于第一通孔。

公开(公告)号：US20160374204A1

公开(公告)日：2016-12-22

申请号：US15053373

申请日：2016-02-25

Applicant: Kabushiki Kaisha Toshiba

Inventor： Yasumichi Miyazaki

IPC: H05K1/18 ,  H05K3/34 ,  H05K1/11

CPC classification number: H05K1/111 ,  H05K3/3442 ,  H05K2201/09381 ,  H05K2201/09663 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/042 ,  Y02P70/611 ,  Y02P70/613

Abstract: According to one embodiment, a circuit board includes a land to which a component is soldered. The land includes a first land to which a solder base is mounted, and a second land integrated with the first land. The second land has a width less than a width of a connection terminal. The solder base provided on the first land melts and flows into a gap between the second and land by capillary action. The component is attached to the circuit board with the solder that has flowed in.

Abstract translation: 根据一个实施例，电路板包括焊接有部件的焊盘。 该焊盘包括安装有焊料基底的第一焊盘和与该焊盘一体化的第二焊盘。 第二平台的宽度小于连接端子的宽度。 在第一土地上提供的焊料基底通过毛细作用熔化并流入第二和第二焊盘之间的间隙。 组件通过已经流入的焊料连接到电路板。

公开(公告)号：US09480141B1

公开(公告)日：2016-10-25

申请号：US14032908

申请日：2013-09-20

Applicant: Junis Hamadeh

Inventor： Junis Hamadeh

IPC: H05K1/02 ,  H01R12/00

CPC classification number: H01R12/00 ,  H05K1/0206 ,  H05K1/021 ,  H05K1/113 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/09463 ,  H05K2201/0959 ,  H05K2201/10106 ,  H05K2201/10401 ,  H05K2201/10416

Abstract: A heat sinking rapid assembly semiconductor package comprising an electrically segmented conductive assembly post. The post is fabricated comprising at least two independent electrically conductive segments separated by an electrically isolating element. An electrical component, such as a semiconductor device, is assembled to an upper portion of the conductive post, wherein each contact of the component is in electrical communication with a respective conductive segment. The post can be mechanically pressed, threaded, or mechanically coupled using any other reasonable mechanical interface into a segmented via or plated-through hole of a printed circuit board (PCB). The electrical segments would be in electrical communication with conductive portions of the segmented via to form a complete electrical circuit between the PCB and the electrical component. A thermally conductive element can be integrated into the post to conduct heat away from the semiconductor device to improve performance and reduce failures related to thermal stress.

Abstract translation: 一种散热快速组装半导体封装，包括电分段的导电组件柱。 该柱被制造成包括由电隔离元件隔开的至少两个独立的导电段。 诸如半导体器件的电气部件被组装到导电柱的上部，其中部件的每个触点与相应的导电部分电连通。 可以使用任何其他合理的机械接口将柱机械地压制，螺纹化或机械耦合到印刷电路板（PCB）的分段通孔或电镀通孔中。 电段将与分段通孔的导电部分电连通，以在PCB和电气部件之间形成完整的电路。 导热元件可以集成到柱中以将热量从半导体器件导出，以提高性能并减少与热应力相关的故障。