公开(公告)号：US3455855A

公开(公告)日：1969-07-15

申请号：US3455855D

申请日：1965-10-22

Applicant: CONAP INC

Inventor： HOUGHTON RUSSELL M ,  MCELROY WILBUR R

IPC: B41M1/12 ,  H05K3/28 ,  C08G41/00 ,  B41M3/08 ,  H05K3/00

CPC classification number: H05K3/285 ,  B41M1/12 ,  H05K2201/09872

公开(公告)号：US11786930B2

公开(公告)日：2023-10-17

申请号：US16466743

申请日：2017-12-12

Applicant: HZO, Inc.

Inventor： Shailendra Vikram Singh ,  Gianfranco Aresta ,  Andrew Simon Hall Brooks ,  Siobhan Marie Woollard ,  Gareth Hennighan

IPC: B05D1/00 ,  B05D7/00 ,  C09D127/20 ,  C09D183/04 ,  H05K3/28 ,  B05D3/04

CPC classification number: B05D1/62 ,  B05D7/50 ,  C09D127/20 ,  C09D183/04 ,  H05K3/285 ,  B05D3/0486 ,  B05D2252/04 ,  B05D2451/00 ,  B05D2518/10 ,  H05K2201/0179 ,  H05K2201/09872 ,  H05K2203/095 ,  H05K2203/1322 ,  H05K2203/1338

Abstract: A method for depositing a protective coating onto a substrate, wherein the protective coating comprises (i) a moisture-barrier layer which is in contact with the substrate and which comprises a first sub-layer, optionally one or more intermediate sub-layers, and a final sub-layer, (ii) a mechanical-protective layer which is inorganic, and (iii) a gradient layer interposing the moisture-barrier layer and the mechanical-protective layer.

公开(公告)号：US20180350780A1

公开(公告)日：2018-12-06

申请号：US16047688

申请日：2018-07-27

Applicant: Infineon Technologies AG

Inventor： Edward Fuergut ,  Holger Doepke ,  Olaf Hohlfeld ,  Michael Juerss

IPC: H01L25/07

CPC classification number: H01L25/072 ,  H01L21/52 ,  H01L21/563 ,  H01L21/565 ,  H01L21/568 ,  H01L23/295 ,  H01L23/3121 ,  H01L23/3135 ,  H01L23/3142 ,  H01L23/552 ,  H01L23/562 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/03462 ,  H01L2224/05647 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48491 ,  H01L2224/73265 ,  H01L2224/83951 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18301 ,  H05K3/282 ,  H05K3/284 ,  H05K2201/09872 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/1377 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099

Abstract: An electronic device package includes a semiconductor chip having a contact pad on a main face of the semiconductor chip, a contact element disposed on the contact pad, a dielectric layer disposed on the semiconductor chip and the contact element, and an encapsulant disposed onto the dielectric layer.

公开(公告)号：US20180220534A1

公开(公告)日：2018-08-02

申请号：US15937172

申请日：2018-03-27

Applicant: TactoTek Oy

Inventor： Mikko HEIKKINEN ,  Jarmo SÄÄSKI ,  Jarkko Torvinen

IPC: H05K1/18 ,  H01L33/52 ,  H01L23/498 ,  H05K1/02 ,  H01L51/00 ,  H01L23/538

CPC classification number: H05K1/186 ,  H01L23/4985 ,  H01L23/5387 ,  H01L33/52 ,  H01L51/0097 ,  H01L2224/1319 ,  H01L2933/005 ,  H05K1/0274 ,  H05K1/0298 ,  H05K1/189 ,  H05K3/284 ,  H05K2201/0129 ,  H05K2201/05 ,  H05K2201/09872 ,  H05K2201/10106 ,  H05K2201/10151 ,  H05K2203/1316 ,  H05K2203/1322

Abstract: A multilayer structure for an electronic device including a flexible substrate film for accommodating electronics; at least one electronic component provided on the substrate film; and a number of conductive traces provided on the substrate film for electrically powering and/or connecting electronics including the at least one electronic component, wherein at least one preferably thermoformed cover is attached to the substrate film on top of the at least one electronic component, the at least one thermoformed cover and the substrate film accommodating the electronics being overmolded with thermoplastic material. The invention also relates to a method for manufacturing a multilayer structure for an electronic device.

公开(公告)号：US20180160525A1

公开(公告)日：2018-06-07

申请号：US15701625

申请日：2017-09-12

Applicant: Kabushiki Kaisha Toshiba ,  Toshiba Infrastructure Systems & Solutions Corporation

Inventor： Yoshiaki SATAKE ,  Shinji TAMAI

IPC: H05K1/02 ,  H05K3/00 ,  H05K3/42

CPC classification number: H05K1/0209 ,  H01L23/552 ,  H01L2924/3025 ,  H05K1/0204 ,  H05K1/0233 ,  H05K3/0061 ,  H05K3/281 ,  H05K3/284 ,  H05K3/3415 ,  H05K3/3426 ,  H05K3/429 ,  H05K7/205 ,  H05K2201/0215 ,  H05K2201/066 ,  H05K2201/095 ,  H05K2201/09581 ,  H05K2201/09872 ,  H05K2201/10689 ,  H05K2203/1311 ,  H05K2203/1316 ,  H05K2203/1322 ,  H05K2203/1438

Abstract: A circuit board device of the embodiment includes: a mount board having an electronic component and a printed circuit board having at least one surface where the electronic component is mounted; a heat path arranged to a position facing the mount surface of the mount board, a sheet arranged on the mount surface, and a resin portion arranged between the sheet and the heat path. A cavity surrounded by the sheet and the mount surface is formed in a step portion between the electronic component and the printed circuit board.

公开(公告)号：US09699917B2

公开(公告)日：2017-07-04

申请号：US14292876

申请日：2014-05-31

Applicant: Cytec Industries Inc.

Inventor： Richard David Jordan, Jr. ,  Thomas C. Scanlon, IV

IPC: C08G18/24 ,  C08G18/48 ,  C08G18/76 ,  C09D175/04 ,  H05K3/28

CPC classification number: H05K3/284 ,  C08G2/10 ,  C08G18/246 ,  C08G18/36 ,  C08G18/4825 ,  C08G18/7664 ,  C09D175/04 ,  H05K3/285 ,  H05K2201/09872 ,  C08G18/10

Abstract: Formulated resin systems containing polymeric flood coat compositions are provided herein and characterized by having an initial mix thixotropic index from 1 to 5, and a gel time from 5 to 15 minutes such that when cured the compositions provide a Shore hardness from 15 A to 90 A, a thickness on horizontal surfaces from 20 mils to 75 mils, and a thickness on vertical surfaces from 4 mils to 20 mils. Electronic circuit assemblies flood coated with such formulated resin systems, and methods for protecting and supporting said assemblies, are also provided.

公开(公告)号：US20170188454A1

公开(公告)日：2017-06-29

申请号：US15459740

申请日：2017-03-15

Applicant: Sridharan Venk ,  Earl Alfred Picard ,  Qi Dai ,  Richard Garner

Inventor： Sridharan Venk ,  Earl Alfred Picard ,  Qi Dai ,  Richard Garner

IPC: H05K1/02

CPC classification number: H05K1/111 ,  F21S4/22 ,  F21V21/005 ,  G06K19/07749 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L33/385 ,  H01L33/44 ,  H01L33/62 ,  H01L2224/291 ,  H01L2224/2919 ,  H01L2224/32227 ,  H01L2224/48227 ,  H01L2224/83424 ,  H01L2224/83439 ,  H01L2224/83444 ,  H01L2224/83447 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/85424 ,  H01L2224/85439 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/97 ,  H01L2924/00014 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1421 ,  H05K1/0209 ,  H05K1/028 ,  H05K1/0296 ,  H05K1/118 ,  H05K1/189 ,  H05K3/0097 ,  H05K3/02 ,  H05K3/28 ,  H05K3/30 ,  H05K2201/051 ,  H05K2201/09381 ,  H05K2201/09445 ,  H05K2201/09727 ,  H05K2201/09736 ,  H05K2201/09872 ,  H05K2201/099 ,  H05K2201/10098 ,  H05K2201/10106 ,  H05K2201/10522 ,  H05K2203/1545 ,  Y02P70/611 ,  Y10T29/4913 ,  H01L2924/014 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A conductor pad and a flexible circuit including a conductor pad are provided. The conductor pad includes a first contact region, a second contact region, and a body portion configured to establish a conductive path between the first contact region and the second contact region. The body portion includes a perimeter edge having at least a first convex segment and a second convex with a first non-convex segment disposed between the first convex segment and the second convex segment. A method of constructing a flexible circuit to facilitate roll-to-roll manufacturing of the flexible circuit is also provided.

公开(公告)号：US09674963B1

公开(公告)日：2017-06-06

申请号：US15173508

申请日：2016-06-03

Applicant: Eric Sari ,  Brian Stumm ,  Roger Plough

Inventor： Eric Sari ,  Brian Stumm ,  Roger Plough

IPC: H05K3/28 ,  B65G43/00 ,  B65G37/00 ,  G05B19/042

CPC classification number: G05B19/0421 ,  B65G43/00 ,  H05K3/0091 ,  H05K3/28 ,  H05K3/287 ,  H05K2201/09872 ,  H05K2203/1361 ,  H05K2203/1366

Abstract: A machine can include a first conveyor configured to receive and convey a circuit assembly; a second conveyor configured to receive and convey a circuit assembly; a first set of opposing side panels adjacent to opposing sides of the first conveyor; a second set of opposing side panels adjacent to opposing sides of the second conveyor; a first mechanism that selectively raises and lowers the first set of opposing side panels; and a second mechanism that selectively raises and lowers the second set of opposing side panels.

公开(公告)号：US20170150613A1

公开(公告)日：2017-05-25

申请号：US15426696

申请日：2017-02-07

Applicant: International Business Machines Corporation

Inventor： Sarah K. CZAPLEWSKI ,  Joseph KUCZYNSKI ,  Jason T. WERTZ ,  Jing ZHANG

IPC: H05K3/28 ,  C09D163/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K3/28 ,  C09D163/00 ,  H05K1/02 ,  H05K1/11 ,  H05K3/0058 ,  H05K3/0079 ,  H05K3/282 ,  H05K3/284 ,  H05K3/288 ,  H05K3/4644 ,  H05K2201/0183 ,  H05K2201/09872 ,  H05K2203/1322

Abstract: In an example, a process for reversibly bonding a conformal coating to a dry film solder mask (DFSM) material is disclosed. The process includes applying a first conformal coating material to a DFSM material. The first conformal coating material includes a first functional group, and the DFSM material includes a second functional group that is different from the first functional group. The process also includes reversibly bonding the first conformal coating material to the DFSM material via a chemical reaction of the first functional group and the second functional group.

公开(公告)号：US20160249457A1

公开(公告)日：2016-08-25

申请号：US15045544

申请日：2016-02-17

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Tae-Hong MIN ,  Myung-Sam KANG ,  Young-Gwan KO ,  Min-Jae SEONG

IPC: H05K1/18 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0298 ,  H01L23/13 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/00 ,  H05K1/113 ,  H05K3/4608 ,  H05K2201/0195 ,  H05K2201/0367 ,  H05K2201/09672 ,  H05K2201/09872 ,  H05K2201/10674

Abstract: A circuit board and an assembly including the circuit board are provided. The circuit board includes a first insulation layer, a first conductive pattern disposed on the first insulation layer, an insulation film disposed on the first conductive pattern, and a second conductive pattern disposed on the insulation film. The insulation film includes an insulation thin film contacting the first conductive pattern, and a function film disposed on the insulation thin film and contacting the second conductive pattern.

Abstract translation: 提供电路板和包括电路板的组件。 电路板包括第一绝缘层，设置在第一绝缘层上的第一导电图案，设置在第一导电图案上的绝缘膜，以及布置在绝缘膜上的第二导电图案。 绝缘膜包括与第一导电图案接触的绝缘薄膜和设置在绝缘薄膜上并与第二导电图案接触的功能膜。