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    Dielectric structure for printed circuit board traces
    171.
    发明申请
    Dielectric structure for printed circuit board traces 失效
    印刷电路板走线的介质结构

    公开(公告)号：US20050082087A1

    公开(公告)日：2005-04-21

    申请号：US10690113

    申请日：2003-10-21

    Applicant: Ehood Geva ,  Todd Takken

    Inventor： Ehood Geva ,  Todd Takken

    IPC: H05K1/02 ,  H05K3/22 ,  H05K7/06

    CPC classification number: H05K1/0219 ,  H05K3/222 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/10371

    Abstract: A trace cover suitable for shielding a conductive trace on a top layer of a circuit board. The trace cover includes a dielectric body disposed substantially over the conductive trace, side shielding perpendicular to the direction of the conductive trace and substantially parallel to the length of the conductive trace, and top shielding disposed on the top surface of the body. The side shielding and top shielding are electrically coupled with the at least one circuit ground of the circuit board.

    Abstract translation: 适用于屏蔽电路板顶层导电迹线的痕迹盖。 迹线盖包括基本上布置在导电迹线上的绝缘体，垂直于导电迹线的方向的侧屏蔽，并且基本上平行于导电迹线的长度，以及设置在主体的顶表面上的顶部屏蔽。 侧面屏蔽和顶部屏蔽电路与电路板的至少一个电路接地电耦合。

    Communication apparatus and method of fabricating the same
    172.
    发明授权
    Communication apparatus and method of fabricating the same 失效
    通信装置及其制造方法

    公开(公告)号：US06876841B1

    公开(公告)日：2005-04-05

    申请号：US09560962

    申请日：2000-04-28

    Applicant: Masaru Kosaka

    Inventor： Masaru Kosaka

    IPC: H04B1/38 ,  H04B1/3822 ,  H04B15/00 ,  H05K1/02 ,  H05K1/14 ,  H05K9/00 ,  H04B1/10

    CPC classification number: H05K9/0032 ,  H04B1/40 ,  H04B15/00 ,  H05K1/0218 ,  H05K1/0237 ,  H05K1/141 ,  H05K2201/0715 ,  H05K2201/2018

    Abstract: A communication apparatus including a radio frequency (RF) circuit module can be reduced in the number of components therefor to reduce the cost for its components and to simplify its fabrication process and thus reduce the cost for manufacturing the same while the RF circuit module can also be shielded reliably. The RF circuit module includes a printed circuit board having an upper surface with a circuit component mounted thereto and a lower surface provided with a shielding conductor of metal. The printed circuit board is fit into a shielding frame to assemble the RF circuit module. The RF circuit module is then turned over and thus mounted on that upper surface of a mother board which is provided with conductors of metal. Such conductors of metal and the frame can shield the RF circuit module.

    Abstract translation: 包括射频（RF）电路模块的通信设备可以减少其组件的数量，以降低其组件的成本并简化其制造过程，并且因此降低了其制造成本，同时RF电路模块也可以 可靠地屏蔽 RF电路模块包括具有安装在其上的电路部件的上表面和设置有金属屏蔽导体的下表面的印刷电路板。 将印刷电路板装配到屏蔽框架中以组装RF电路模块。 然后将RF电路模块翻转并由此安装在设置有金属导体的母板的上表面上。 金属和框架的这种导体可以屏蔽RF电路模块。

    Wired circuit board
    173.
    发明申请
    Wired circuit board 有权
    有线电路板

    公开(公告)号：US20040246626A1

    公开(公告)日：2004-12-09

    申请号：US10859150

    申请日：2004-06-03

    Inventor： Shuichi Wakaki ,  Tadao Ohkawa ,  Yasuhito Ohwaki

    IPC: G11B005/48

    CPC classification number: G11B5/486 ,  H05K1/0237 ,  H05K1/056 ,  H05K3/0058 ,  H05K3/363 ,  H05K2201/0367 ,  H05K2201/0715 ,  H05K2201/093 ,  H05K2201/0969

    Abstract: A wired circuit board that can control characteristic impedance at connection points between the read wire and write wire of a suspension board with circuit and terminal portions of the wired circuit board connected thereto with a simple structure, to improve signal transmission efficiency for fine pitch wiring or for high frequency signal. A conductive board 25 is adhesively bonded to an insulating base layer 18 of the wired circuit board 1 at one side thereof opposite to the other side on which a suspension-board-side connection terminal portion 11 having a first terminal portion 13 to connect with a read wire 6R of a suspension board with circuit 3 and a second terminal portion 14 to connect with a write wire 6W of the suspension board with circuit 3 is formed, in such a relation that an opening 27 can correspond in position to either of the first terminal portion 13 and the second terminal portion 14, and a stiffener board 24 is adhesively bonded to the conductive board 25 via an adhesive layer 28.

    Abstract translation: 一种布线电路板，其能够以简单的结构控制悬挂板的读取线和写入线之间的连接点处的特性阻抗，其中电路和与其连接的布线电路板的端子部分，以提高细间距布线的信号传输效率或 用于高频信号。 导电板25粘合到布线电路板1的绝缘基底层18的与另一侧相对的一侧，在该侧上具有第一端子部分13的悬挂板侧连接端子部分11与其连接 形成具有电路3的悬架板的读取线6R和与电路3与悬挂板的写入线6W连接的第二端子部14，其中开口27可以位于第一 端子部13和第二端子部14，并且加强板24经由粘合剂层28粘合到导电板25上。

    FILTERING ELECTROMAGNETIC INTERFERENCE FROM LOW FREQUENCY TRANSMISSION LINES AT A DEVICE ENCLOSURE
    174.
    发明申请
    FILTERING ELECTROMAGNETIC INTERFERENCE FROM LOW FREQUENCY TRANSMISSION LINES AT A DEVICE ENCLOSURE 失效
    从设备外壳的低频传输线滤波电磁干扰

    公开(公告)号：US20040219837A1

    公开(公告)日：2004-11-04

    申请号：US10426229

    申请日：2003-04-30

    Inventor： Andrew Michael Cherniski ,  Kirk Yates

    IPC: H01R013/66

    CPC classification number: H01R13/719 ,  H01R13/652 ,  H01R24/78 ,  H01R2103/00 ,  H01R2201/06 ,  H05K1/0231 ,  H05K1/181 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/09809 ,  H05K2201/10189

    Abstract: An electrical device having an enclosure in which noise is parasitically induced in a wire located in the interior of the enclosure is disclosed. The electrical device has an entry connector for mating the wire with an external connector at which a transmission line terminates for preventing the induced noise from being emitted from the device enclosure via the transmission line. The electrical device comprises a printed circuit board (PCB) adapted to be mounted adjacent to an opening in a wall of the enclosure, a receptacle, integral with the PCB, configured to mate with the external connector, a first conductive path coupling the transmission line with the wire when mated, and capacitors mounted on the printed circuit board radially disposed around the receptacle and adapted to be electrically coupled to the external connector when mated. The electrical device further comprises a second conductive path coupling the capacitors to a low potential sink.

    Abstract translation: 公开了一种具有外壳的电气设备，其中噪声在位于外壳内部的导线中被寄生地感应。 电气设备具有用于将导线与外部连接器配合的入口连接器，在该连接器处传输线终止，用于防止感应噪声经由传输线从设备外壳发射。 电气设备包括适于安装在外壳壁上的开口附近的印刷电路板（PCB），与该PCB一体的插座，被配置为与外部连接器相配合，第一导电路径将传输线 并且电容器安装在放射状设置在插座周围的印刷电路板上，并且适合于在配合时电耦合到外部连接器。 电气设备还包括将电容器耦合到低电位宿的第二导电路径。

    High speed electronics interconnect and method of manufacture
    176.
    发明申请
    High speed electronics interconnect and method of manufacture 有权

    公开(公告)号：US20040173880A1

    公开(公告)日：2004-09-09

    申请号：US10793363

    申请日：2004-03-04

    Inventor： Dutta Achyut

    IPC: H01L029/40 ,  H01L023/12

    CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/2005 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0236 ,  H05K1/024 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0313 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09681 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/05599

    Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects, respectively. According to this invention, the interconnection system has also lower effective dielectric constant, which would help to reduce the signal propagation delay and reduce the signal skews. The interconnect systems consists of the signal line, inhomogeneous dielectric system consisting of the homogeneous dielectric layer and conducting or metal plans having 1-diemensioanl or 2-dimensioanl arrays in structure, located into the homogeneous dielectric layer, and the ground plan. The signal line proposed in this invention could be any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations. Alternatively, the interconnect systems consists of the signal line, homogeneous dielectric layer, and the ground plan which is in 1-dimensional or 2-dimensional array in structure. The interconnect system based on the fundamental techniques provided in this invention, can be used for on-chip interconnects where the high speed electronics devices are connected by the signal line laid on the oxide or dielectric material. Again, the interconnect system based on the fundamental techniques provided in this invention, can also be used for off-chip interconnects (chip-to-chip interconnects), where the whole portion or portion of the PCB on which high speed chips are to be connected, are having the dielectric system with opened trench or slot to reduce the microwave loss. High scale chip-to-chip interconnection using of the multilayered PCB is possible. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables. The main advantages of this invention are to make high speed interconnects systems for on-chip and off-chip interconnects. More over, this fundamental technology is also used for the high sped die-package, high speed connector, and high speed cables where conventional manufacturing technology can be used and yet to increase the bandwidth of the interconnects.

    High speed electronics interconnect and method of manufacture
    177.
    发明申请
    High speed electronics interconnect and method of manufacture 有权

    公开(公告)号：US20040173822A1

    公开(公告)日：2004-09-09

    申请号：US10793576

    申请日：2004-03-04

    Inventor： Achyut Dutta

    IPC: H01L027/10

    CPC classification number: H01L23/66 ,  H01L23/5383 ,  H01L25/0655 ,  H01L2223/6627 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/13091 ,  H01L2924/1903 ,  H01L2924/19032 ,  H01L2924/19033 ,  H01L2924/3011 ,  H01P1/2005 ,  H01P3/08 ,  H05K1/0224 ,  H05K1/0236 ,  H05K1/024 ,  H05K1/0253 ,  H05K1/0298 ,  H05K1/0306 ,  H05K1/0313 ,  H05K2201/0187 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09036 ,  H05K2201/09063 ,  H05K2201/09681 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/05599

    Abstract: Fundamental interconnect systems for connecting high-speed electronics elements are provided. Interconnect system has the means, which could reduce the microwave loss by reducing the effective dielectric loss and dielectric constant of the interconnect system, and increase the bandwidth of the interconnects and also reduce the signal propagation delay, respectively. Ideally, the speed of the electrical signal on the signal line can be reached to speed of the light in the air, and the bandwidth can be reached to closer to the optical fiber. The interconnect systems consists of the signal line, dielectric system with opened trench or slot filled up with the air or lower dielectric loss material, and the ground plan. The signal line proposed in this invention could be made any type of signal line configuration for example, microstripline, strip line or coplanar line. The signal line can also be made as single ended or differential pairs of any configurations. The interconnect system based on the fundamental techniques provided in this invention, can be used for on-chip interconnects where the high speed electronics devices are connected by the signal line laid on the oxide or dielectric material. Again, the interconnect system based on the fundamental techniques provided in this invention, can also be used for off-chip interconnects (chip-to-chip interconnects), where the whole portion or portion of the PCB on which high speed chips are to be connected, are having the dielectric system with opened trench or slot to reduce the microwave loss. High scale chip-to-chip interconnection using of the multilayered PCB is possible. The fundamental techniques provided in this invention can also be used for high-speed connectors and high-speed cables. The main advantages of this invention are to make high speed interconnects systems for on-chip and off-chip interconnects. More over, this fundamental technology is also used for the high sped die package, high speed connector, and high speed cables where conventional manufacturing technology can be used and yet to increase the bandwidth of the interconnects.

    Low loss, high density array interconnection
    180.
    发明申请
    Low loss, high density array interconnection 有权
    低损耗，高密度阵列互连

    公开(公告)号：US20040125577A1

    公开(公告)日：2004-07-01

    申请号：US10331032

    申请日：2002-12-27

    Inventor： Patrizio Vinciarelli ,  Charles I. McCauley ,  Paul V. Starenas

    IPC: H05K001/18

    CPC classification number: H05K1/0219 ,  H01L23/492 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49844 ,  H01L23/50 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01078 ,  H01L2924/01322 ,  H01L2924/13091 ,  H05K1/113 ,  H05K3/3436 ,  H05K2201/0715 ,  H05K2201/09618 ,  H05K2201/10734 ,  H01L2224/0401

    Abstract: An interconnect architecture in which a substrate such as a printed circuit board includes multiple conductive layers separated by one or more interposed insulating layers, the conductive layers being adapted to receive a high density array of interconnect elements such as a ball grid array (BGA). In certain preferred embodiments, a printed circuit board may provide a very low resistance interconnect forming the drain and source terminals of a lateral power MOSFET device incorporating a high density array of alternating source and drain interconnect elements, such as a BGA. In such embodiments, source and drain currents may be routed on different conductive layers separated by one or more interposed insulating layers. The upper conductive layer may include laterally non-conductive regions accommodating conductive columns that are connected to the lower conductive layer.

    Abstract translation: 一种互连架构，其中诸如印刷电路板的衬底包括由一个或多个插入的绝缘层分隔的多个导电层，所述导电层适于接收诸如球栅阵列（BGA）的互连元件的高密度阵列。 在某些优选实施例中，印刷电路板可以提供形成横向功率MOSFET器件的漏极和源极端子的非常低的电阻互连，其包括交替的源极和漏极互连元件（例如BGA）的高密度阵列。 在这样的实施例中，源极和漏极电流可以被布置在由一个或多个插入的绝缘层分开的不同导电层上。 上导电层可以包括容纳连接到下导电层的导电柱的横向非导电区域。

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