公开(公告)号：US5455393A

公开(公告)日：1995-10-03

申请号：US159234

申请日：1993-11-30

Applicant: Tutomu Ohshima ,  Hidebumi Ohnuki ,  Ryo Maniwa

Inventor： Tutomu Ohshima ,  Hidebumi Ohnuki ,  Ryo Maniwa

IPC: H05K3/34 ,  H05K1/02 ,  H05K1/11 ,  H05K3/00 ,  H05K3/46 ,  H05K1/00

CPC classification number: H05K1/0221 ,  H05K1/112 ,  H05K3/465 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2203/0733 ,  H05K3/0023 ,  H05K3/3468 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A multilayered printed wiring board includes a plurality of inner layer circuits, ground layers, first insulating layers, a second insulating layer, a surface layer circuit, and a parts mounting pad. The inner layer circuits are arranged parallel to each other in a flat manner in at least one inner layer. The ground layers are formed on and under the inner layer circuits to sandwich the inner layer circuits. The first insulating layers are respectively formed between the ground layers and the inner layer circuits to insulate the inner layer circuits from each other and the inner layer circuits from the ground layers. The second insulating layer is formed at least on an uppermost one of the ground layers and serving as a surface layer. The surface layer circuit is selectively formed on the second insulating layer. The parts mounting pad is formed at a predetermined region on the second insulating layer, has a recessed portion for fitting a lead portion of a mounting part therein, and is connected to the surface layer circuit. A method of manufacturing this printed wiring board is also disclosed.

Abstract translation: 多层印刷电路板包括多个内层电路，接地层，第一绝缘层，第二绝缘层，表面层电路和部件安装焊盘。 内层电路在至少一个内层中以平坦的方式彼此平行地布置。 接地层形成在内层电路之上和之下，以夹住内层电路。 第一绝缘层分别形成在接地层和内层电路之间，以使内层电路彼此隔离，内层电路与接地层绝缘。 第二绝缘层至少形成在最上层的一层接地层中并用作表面层。 表层电路选择性地形成在第二绝缘层上。 零件安装垫形成在第二绝缘层上的预定区域，具有用于将安装部件的引线部分嵌入其中的凹部，并连接到表面层电路。 还公开了制造该印刷线路板的方法。

公开(公告)号：US5130768A

公开(公告)日：1992-07-14

申请号：US624034

申请日：1990-12-07

Applicant: Andrew L. Wu ,  Martin W. Czekalski

Inventor： Andrew L. Wu ,  Martin W. Czekalski

IPC: H01L23/40 ,  H01L23/473 ,  H01L23/498 ,  H01L23/538 ,  H05K1/14 ,  H05K3/34 ,  H05K3/36

CPC classification number: H05K1/141 ,  H01L23/4006 ,  H01L23/473 ,  H01L23/49811 ,  H01L23/5385 ,  H01L2023/4062 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K3/3421 ,  H05K3/368

Abstract: A compact high-density packaging arrangement for high-performance semiconductor devices includes a plurality of high-performance semiconductor chips connected to a multilayer daughter substrate member using a bare chip assembly technique known as bonded pin technology. Internal bonded pins are formed on bonding pads of the chips and soldered to conductive pads in solder wells located on the daughter substrate to provide a first level of interconnection for the chips. A larger, multilayer mother substrate member has a plurality of apertures formed in one surface thereof. These apertures are terminated by a top side of a metallized base layer of the substrate. An opposite surface of the mother substrate, i.e. a bottom side of the base layer, is affixed in thermal conductive relation to a metallic cold plate adapted for receiving a cooling fluid. External bonded pins are formed on bonding pads of the daughter substrate and inserted into corresponding solder wells located on the mother substrate. Concurrently, the bare chips are situated into the apertures in intimate thermal conductive relation to the cold plate via the metallized base layer. The pins are then soldered to conductive pads in the solder wells, thereby providing a second level of chip interconnection when other chip-populated daughter substrates are mounted thereon.

Abstract translation: 用于高性能半导体器件的紧凑型高密度封装装置包括使用称为接合引脚技术的裸芯片组装技术连接到多层子衬底构件的多个高性能半导体芯片。 内部接合引脚形成在芯片的焊盘上，并焊接到位于子基板上的焊料阱中的导电焊盘，以提供芯片的第一级互连级别。 较大的多层母体衬底构件在其一个表面中形成有多个孔。 这些孔由衬底的金属化基底层的顶侧终止。 母基板的相对表面，即基底层的底侧，与适于接收冷却流体的金属冷板以导热关系固定。 外部接合引脚形成在子基板的焊盘上并插入位于母基板上的相应的焊接阱中。 同时，裸芯片通过金属化基底层与冷板以紧密的导热关系位于孔中。 然后将引脚焊接到焊料阱中的导电焊盘，从而当安装其上的其它芯片填充的子基板时提供第二级芯片互连。

公开(公告)号：US5055637A

公开(公告)日：1991-10-08

申请号：US434427

申请日：1989-11-13

Applicant: George R. Hagner

Inventor： George R. Hagner

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H05K3/08 ,  H05K3/10 ,  H05K3/18 ,  H05K3/20 ,  H05K3/24 ,  H05K3/34 ,  H05K3/42

CPC classification number: H05K3/20 ,  H05K1/111 ,  H05K1/183 ,  H05K3/08 ,  H05K3/107 ,  H05K3/3473 ,  H05K2201/0129 ,  H05K2201/0376 ,  H05K2201/09036 ,  H05K2201/09118 ,  H05K2201/09472 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2201/09981 ,  H05K2201/10636 ,  H05K2201/10681 ,  H05K2203/0117 ,  H05K2203/0278 ,  H05K2203/042 ,  H05K2203/0726 ,  H05K2203/0769 ,  H05K3/0094 ,  H05K3/108 ,  H05K3/184 ,  H05K3/244 ,  H05K3/3421 ,  H05K3/3442 ,  H05K3/3452 ,  H05K3/42 ,  H05K3/426 ,  Y02P70/611

Abstract: Circuit boards with imbedded traces, which may form grooves or trenches are provided. The traces may be at least partially filled with a reflowable conductive material such as solder. The grooves may be selectively furnished with solder while other regions may be empty or void of solder. In assembling electronic components, with or without extended leads, such as surface mount integrated circuits or chips, to the solder core circuit boards, the leads may be placed within the regions of the grooves without solder (contact regions) and then the circuit board may be heated selectively or as a whole to reflow the solder to the bonding or contacting regions to bond the traces to the leads upon cooling. Circuit boards having surface mount devices on both sides may be formed in this manner. Further, tape automated bonded or TAB mounted devices may be directly placed into and bonded to the traces or solder core circuit boards with minimum exposure of the excised TAB leads prior to assembly. In one form, the grooves are plated with copper before they are filled with solder. Alternatively, the solder may be present only in cavities or pockets next to the contact regions where the component lead will connect with the conductive material pattern.

Abstract translation: 提供具有嵌入痕迹的电路板，其可以形成凹槽或沟槽。 迹线可以至少部分地填充有可回流的导电材料，例如焊料。 凹槽可以选择性地装备有焊料，而其它区域可能是空的或者没有焊料。 在组装电子部件的情况下，将带有或不具有延伸引线（例如表面贴装集成电路或芯片）的电子部件组装到焊料芯电路板上，可以将引线放置在槽的区域内而不用焊料（接触区域），然后电路板可以 被选择性地或作为整体加热以将焊料回流到接合或接触区域，以在冷却时将迹线结合到引线。 可以以这种方式形成具有两侧表面安装装置的电路板。 此外，胶带自动粘合或TAB安装的装置可以在组装之前以最小的切割的TAB导线的暴露直接放置到轨迹或焊芯电路板中并结合到轨迹或焊芯电路板。 在一种形式中，在填充有焊料之前，将槽镀铜。 或者，焊料可以仅存在于部件引线将与导电材料图案连接的接触区域旁边的腔或袋中。

公开(公告)号：US5036431A

公开(公告)日：1991-07-30

申请号：US393013

申请日：1989-08-11

Applicant: Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

Inventor： Kazumasa Adachi ,  Shinji Takahashi ,  Kimitaka Hirabayashi

IPC: H05K1/11 ,  H05K1/14 ,  H05K3/00 ,  H05K3/34 ,  H05K3/36 ,  H05K3/46

CPC classification number: H05K1/114 ,  H05K1/141 ,  H05K1/144 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09627 ,  H05K2201/10303 ,  H05K2201/10318 ,  H05K2201/10477 ,  H05K2201/10689 ,  H05K2201/10871 ,  H05K3/0047 ,  H05K3/3447 ,  H05K3/368 ,  H05K3/4652

Abstract: A package for surface-mounted components according to the present invention includes a first board which includes contact portions formed on a front face side thereof for mounting the components to be surface-mounted thereon, and first through-holes electrically contiguous with the contact portions; a second board includes conductor pins provided on a rear face side thereof for establishing continuity with another board and second through-holes electrically contiguous with the conductor pins; and a conductor layer interposed between the first and second boards by which the first through-holes in the first board side and the second through-holes in the second board side are mutually electrically connected.

Abstract translation: 根据本发明的用于表面安装部件的包装包括第一板，其包括形成在其正面侧上的接触部分，用于安装要表面安装的部件，以及与接触部分电连接的第一通孔; 第二板包括设置在其背面侧的导体销，用于与另一个板形成连续性，并且与导体引脚电连接的第二通孔; 以及介于第一和第二板之间的导体层，第一板侧的第一通孔和第二板侧的第二通孔相互电连接。

公开(公告)号：US4758459A

公开(公告)日：1988-07-19

申请号：US7640

申请日：1987-01-28

Applicant: Mahendra C. Mehta

Inventor： Mahendra C. Mehta

IPC: H05K1/00 ,  H05K1/11 ,  H05K1/18 ,  H05K3/32 ,  H05K3/34 ,  H05K3/36 ,  B32B3/10 ,  C04B35/00 ,  H01K3/22 ,  H05K7/10

CPC classification number: H05K3/366 ,  H05K1/119 ,  H05K1/183 ,  H05K3/326 ,  H05K1/0284 ,  H05K1/117 ,  H05K1/18 ,  H05K2201/09036 ,  H05K2201/09045 ,  H05K2201/09081 ,  H05K2201/09118 ,  H05K2201/09472 ,  H05K2201/1059 ,  H05K3/3442 ,  Y10S428/901 ,  Y10T29/49158 ,  Y10T428/24273 ,  Y10T428/24917

Abstract: A circuit board is molded of a heat resistant synthetic resin. Component mounting positions are formed at the time of molding, the mounting positions comprising formations, such as recesses or protrusions, on at least one surface. A circuit pattern is formed on at least one surface and the circuit pattern extends to and over a surface of each formation. A circuit board can be planar or non-planar and be of any desired shape, not necessarily rectangular.

Abstract translation: 电路板由耐热合成树脂模制而成。 在成型时形成组件安装位置，在至少一个表面上的安装位置包括诸如凹槽或突起的地层。 电路图案形成在至少一个表面上，并且电路图案延伸到每个结构的表面上和上方。 电路板可以是平面的或非平面的，并且具有任何期望的形状，不一定是矩形的。

公开(公告)号：US4697204A

公开(公告)日：1987-09-29

申请号：US516451

申请日：1983-07-22

Applicant: Tsunemasa Mita ,  Ryoki Katoh ,  Soichi Sekimoto ,  Yoshiyuki Shiratsuki ,  Hiroshi Arisawa

Inventor： Tsunemasa Mita ,  Ryoki Katoh ,  Soichi Sekimoto ,  Yoshiyuki Shiratsuki ,  Hiroshi Arisawa

IPC: H01L23/12 ,  H01L23/13 ,  H01L23/498 ,  H05K3/34 ,  H01L23/02

CPC classification number: H01L23/13 ,  H01L23/498 ,  H05K3/3442 ,  H01L2924/0002 ,  H05K2201/09472 ,  H05K2201/10719 ,  H05K2201/10727 ,  Y02P70/613

Abstract: A leadless chip carrier is constructed in such a manner that each of the electrode terminals is made to be recessed from the insulation layer of the bottom surface of the carrier so as to have a difference in level between the bottom surface and at least a part of the electrode terminal. Because of such construction, when the electrode terminals are bonded to the conductors of the printed circuit board in the reflowing method, molten solder is collected in the recessed portions of the electrode terminals besides each portion of the insulation layer positioned between the electrode terminals prevents flowing of the molten solder in the recessed portion, so that strength and reliability in the bonding are remarkably improved.

Abstract translation: 无引线芯片载体被构造成使得每个电极端子被制成从载体的底表面的绝缘层凹陷，以便在底表面和至少一部分 电极端子。 由于这样的结构，当电极端子以回流方式接合到印刷电路板的导体时，熔融焊料被收集在电极端子的凹陷部分中，除了位于电极端子之间的绝缘层的每个部分都防止流动 的凹陷部分中的熔融焊料，从而显着提高了接合中的强度和可靠性。

公开(公告)号：US3832769A

公开(公告)日：1974-09-03

申请号：US14698471

申请日：1971-05-26

Applicant: MINNESOTA MINING & MFG

Inventor： OLYPHANT M ,  ROHLOFF R

IPC: H01L21/60 ,  H01L23/495 ,  H01L23/498 ,  H01L23/538 ,  H01L49/02 ,  H05K1/00 ,  H05K1/11 ,  H05K3/40 ,  H05K3/42 ,  H05K3/32 ,  H05K3/36

CPC classification number: H05K1/113 ,  H01L23/49572 ,  H01L23/4985 ,  H01L23/5384 ,  H01L24/81 ,  H01L49/02 ,  H01L2224/16237 ,  H01L2224/81801 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H05K1/0393 ,  H05K3/4038 ,  H05K3/423 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09563 ,  H05K2201/10674 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A method for mounting semiconductor chips to printed circuitry via conductive columns which extend through the dielectric substrate and electrically communicate with a predetermined pattern of conductive leads on the opposite surface of the substrate. Printed circuitry useful for practicing the method is also provided.

Abstract translation: 一种通过导电柱将半导体芯片安装到印刷电路上的方法，所述导电柱延伸穿过电介质基片并与衬底的相对表面上的预定图案的导电引线电连通。 还提供了用于实施该方法的印刷电路。

公开(公告)号：US3316458A

公开(公告)日：1967-04-25

申请号：US42891365

申请日：1965-01-29

Applicant: HUGHES AIRCRAFT CO

Inventor： JENNY DIETRICH A

IPC: H01L23/13 ,  H05K1/18 ,  H05K3/40

CPC classification number: H01L23/13 ,  H01L2224/16225 ,  H05K1/183 ,  H05K3/4092 ,  H05K2201/09036 ,  H05K2201/09472 ,  Y10T29/4913

公开(公告)号：US20240244762A1

公开(公告)日：2024-07-18

申请号：US18410477

申请日：2024-01-11

Applicant: IBIDEN CO., LTD.

Inventor： Nobuhisa KURODA ,  Naoya MURAKAMI

IPC: H05K3/44 ,  H05K1/11 ,  H05K3/10 ,  H05K3/28

CPC classification number: H05K3/44 ,  H05K1/115 ,  H05K3/103 ,  H05K3/284 ,  H05K2201/0212 ,  H05K2201/09472

Abstract: A wiring substrate includes a core substrate having a cavity penetrating through the substrate, an electronic component accommodated in the cavity such that the component is positioned closer to a first surface of the substrate than a second surface of the substrate, a sealing resin filling the cavity of the substrate such that the sealing resin is covering a surface of the component on a second surface side of the substrate and that the cavity of the substrate has a portion not filled with the sealing resin on the second surface side of the substrate, and resin insulating layers including a first resin insulating layer laminated on the first surface of the substrate and a second resin insulating layer laminated on the second surface of the substrate such that a portion of the second resin insulating layer is filling the portion of the cavity not filled with the sealing resin.

公开(公告)号：US11990438B2

公开(公告)日：2024-05-21

申请号：US17984748

申请日：2022-11-10

Applicant: X Display Company Technology Limited

Inventor： Carl Prevatte ,  Christopher Bower ,  Ronald S. Cok ,  Matthew Meitl

IPC: H01L23/00 ,  H01L21/48 ,  H05K1/11 ,  H05K3/30 ,  H05K3/34

CPC classification number: H01L24/11 ,  H01L24/08 ,  H01L24/13 ,  H01L24/14 ,  H01L24/17 ,  H05K1/112 ,  H05K3/3436 ,  H01L21/4803 ,  H01L21/4846 ,  H01L2224/1144 ,  H01L2224/11466 ,  H01L2224/13017 ,  H01L2224/13023 ,  H01L2224/1357 ,  H01L2224/1403 ,  H01L2224/1412 ,  H01L2224/1418 ,  H01L2224/16227 ,  H01L2224/1624 ,  H01L2224/17107 ,  H01L2924/12041 ,  H01L2924/12043 ,  H01L2924/12044 ,  H01L2924/1304 ,  H05K3/305 ,  H05K2201/09409 ,  H05K2201/09472 ,  H05K2201/0979 ,  H05K2201/10143 ,  H01L2924/12041 ,  H01L2924/00012 ,  H01L2924/12044 ,  H01L2924/00012 ,  H01L2924/12043 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012

Abstract: A component includes a plurality of electrical connections on a process side opposed to a back side of the component. Each electrical connection includes an electrically conductive multi-layer connection post protruding from the process side. A printed structure includes a destination substrate and one or more components. The destination substrate has two or more electrical contacts and each connection post is in contact with, extends into, or extends through an electrical contact of the destination substrate to electrically connect the electrical contacts to the connection posts. The connection posts or electrical contacts are deformed. Two or more connection posts can be electrically connected to a common electrical contact.