公开(公告)号：US06495239B1

公开(公告)日：2002-12-17

申请号：US09458291

申请日：1999-12-10

Applicant: Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

Inventor： Anilkumar C. Bhatt ,  Stephen J. Fuerniss ,  Roy H. Magnuson ,  Voya R. Markovich

IPC: B32B310

CPC classification number: B32B7/04 ,  B32B27/26 ,  B32B27/32 ,  B32B2250/40 ,  B32B2305/72 ,  H05K3/0023 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4641 ,  H05K2201/09509 ,  H05K2201/09536 ,  Y10S428/901 ,  Y10T428/24273 ,  Y10T428/28 ,  Y10T428/31511

Abstract: A dielectric structure, wherein two fully cured photoimageable dielectric (PID) layers of the structure are nonadhesively interfaced by a partially cured PID layer. The partially cured PID layer includes a power plane sandwiched between a first partially cured PID sheet and a second partially cured PID sheet. The fully cured PID layers each include an internal power plane, a plated via having a blind end conductively coupled to the internal power plane, and a plated via passing through the fully cured PID layer. The dielectric structure may further include a first PID film partially cured and nonadhesively coupled to one of the fully cured PID layers. The dialectric structure may further include a second PID film partially cured and nonadhesively coupled to the other fully cured PID layer.

Abstract translation: 一种电介质结构，其中该结构的两个完全固化的可光成像电介质（PID）层通过部分固化的PID层非粘性地接合。 部分固化的PID层包括夹在第一部分固化的PID片和第二部分固化的PID片之间的动力平面。 完全固化的PID层各自包括内部电源平面，具有导电耦合到内部电源平面的盲端的电镀通孔以及穿过完全固化的PID层的电镀通孔。 电介质结构还可以包括部分固化并非粘性地耦合到完全固化的PID层之一的第一PID膜。 所述方程式结构还可以包括部分固化并非粘性地耦合到另一完全固化的PID层的第二PID膜。

公开(公告)号：US20020182958A1

公开(公告)日：2002-12-05

申请号：US09962126

申请日：2001-09-26

Applicant: Fujitsu Limited

Inventor： Motoaki Tani ,  Nobuyuki Hayashi ,  Hiroyuki Machida ,  Takeshi Ishitsuka ,  Yasuo Yamagishi

IPC: B32B003/00 ,  B32B005/02 ,  B32B009/00 ,  B32B027/04 ,  B32B027/12 ,  B32B017/02 ,  B32B027/38 ,  B32B017/04 ,  D03D015/08 ,  D03D017/00

CPC classification number: H05K1/0366 ,  B32B15/04 ,  B32B17/04 ,  B32B27/38 ,  B32B37/0015 ,  B32B2457/08 ,  D03D15/08 ,  H05K3/4602 ,  H05K2201/0209 ,  H05K2201/029 ,  H05K2201/09536 ,  Y10T428/24917 ,  Y10T442/2008 ,  Y10T442/2041 ,  Y10T442/2049 ,  Y10T442/209 ,  Y10T442/2418 ,  Y10T442/2475 ,  Y10T442/2926 ,  Y10T442/2951 ,  Y10T442/2992 ,  Y10T442/3008

Abstract: A multilayer printed wiring board includes a core member including a plurality of glass clothes impregnated with a resin. Each of the glass clothes is woven with glass yarns each of which includes a bundle of glass filaments. One or more buildup layers are laminated on one or each surface of the core member. The core member has an elastic modulus which is no less than 100 times that of the buildup layer at 240null C.

Abstract translation: 多层印刷线路板包括：芯体，其包括浸渍有树脂的多个玻璃衣服。 每个玻璃衣服都用玻璃纱编织，每条玻璃纱都包括一束玻璃丝。 一个或多个堆积层层压在芯构件的一个或每个表面上。 芯构件的弹性模量不小于在240℃下积聚层的弹性模量的100倍。

公开(公告)号：US06441319B1

公开(公告)日：2002-08-27

申请号：US09749470

申请日：2000-12-28

Applicant: Martin R. Handforth ,  Herman Kwong ,  Richard R. Goulette ,  Rolf G. Meier

Inventor： Martin R. Handforth ,  Herman Kwong ,  Richard R. Goulette ,  Rolf G. Meier

IPC: H01R909

CPC classification number: H05K3/4046 ,  H01P1/047 ,  H05K1/024 ,  H05K1/0298 ,  H05K2201/0187 ,  H05K2201/09536 ,  H05K2201/10924 ,  H05K2203/1446 ,  Y10T29/49126 ,  Y10T29/49165

Abstract: A technique for connecting signal tracks within a multi-layer substrate is disclosed. In one embodiment, the technique is realized by providing an opening in a substrate and fitting an inserted component into the opening. The inserted component comprises a dielectric block mounted to a lead frame. The lead frame is conductive such that a signal layer formed between the inserted component and the substrate connects signal tracks on multiple signal layers of the substrate.

Abstract translation: 公开了一种用于连接多层衬底内的信号轨道的技术。 在一个实施例中，该技术通过在基板中提供开口并将插入的部件装配到开口中来实现。 插入的部件包括安装到引线框的介质块。 引线框架是导电的，使得形成在插入部件和衬底之间的信号层连接衬底的多个信号层上的信号轨道。

公开(公告)号：US20020100608A1

公开(公告)日：2002-08-01

申请号：US10003103

申请日：2001-12-06

Applicant: Hoya Corporation

Inventor： Takashi Fushie ,  Takeshi Kagatsume ,  Shigekazu Matsui

IPC: H05K001/03

CPC classification number: H05K3/426 ,  H01L23/5384 ,  H01L2924/0002 ,  H01L2924/09701 ,  H05K1/0306 ,  H05K3/388 ,  H05K3/4602 ,  H05K3/4605 ,  H05K3/467 ,  H05K2201/0154 ,  H05K2201/0175 ,  H05K2201/0179 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959 ,  Y10T29/49165 ,  Y10T428/24926 ,  H01L2924/00

Abstract: A multilayer printed wiring board which permits the formation of fine wiring patterns, thereby increasing the density of wiring patterns. Using photosensitive glass having a coefficient of thermal expansion close to that of a copper film as a core substrate, a through hole is formed in the photosensitive glass by photolithography, a sputtering silicon oxide layer and a sputtering silicon nitride layer are formed to prevent leak of alkali metal ions from the photosensitive glass, a sputtering chromium layer, a sputtering chromium-copper layer and a sputtering copper layer are formed to enhance the adhesion strength between the copper film and the sputtering silicon oxide layer, and a copper film of 1 to 20 nullm thick is formed. With resin filled into the interior of the through hole, a wiring layer is patterned by etching, an insulating layer is formed, and the surface is covered with a surface treatment layer and a cover coat.

Abstract translation: 允许形成精细布线图案的多层印刷布线板，从而增加布线图案的密度。 使用具有与铜膜接近的热膨胀系数的感光性玻璃作为芯基板，通过光刻在感光性玻璃中形成通孔，形成溅射氧化硅层和溅射氮化硅层，以防止泄漏 形成来自感光玻璃的碱金属离子，溅射铬层，溅射铬 - 铜层和溅射铜层，以提高铜膜和溅射氧化硅层之间的粘合强度，并使铜膜为1〜20 形成了厚厚的妈妈。 当树脂填充到通孔的内部时，通过蚀刻对布线层进行图案化，形成绝缘层，并且表面被表面处理层和覆盖层覆盖。

公开(公告)号：US06426011B1

公开(公告)日：2002-07-30

申请号：US09540412

申请日：2000-03-31

Applicant: Takashi Katoh

Inventor： Takashi Katoh

IPC: H05K342

CPC classification number: H05K3/4623 ,  H05K3/0094 ,  H05K3/427 ,  H05K3/4602 ,  H05K2201/0347 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2203/0353

Abstract: A method of making a printed circuit board whereby a fine wiring pattern can be formed. A through hole is formed in a substrate, both surfaces of the substrate being covered with copper foil. The substrate is treated with a catalyst and plated with copper. The through hole is filled with an insulating material, and the copper layer on the substrate is etched so that the catalyst layer is not exposed, leaving a thinned copper layer. Then, the substrate surfaces are ground and leveled by removing any projecting insulating material. Thereafter, another copper layer is deposited on the surface of the substrate, including surface regions on the fill material and is circuitized to form a wiring pattern. Since the catalyst layer is not exposed when the copper layer on the substrate is thinned, a fine wiring pattern can be obtained without the problem of subsequent peeling of the wiring conductors, or the entrapment of air.

Abstract translation: 一种制造印刷电路板的方法，由此可以形成精细的布线图案。 在基板上形成通孔，基板的两面被铜箔覆盖。 用催化剂处理基板并镀上铜。 通孔填充有绝缘材料，并且蚀刻基板上的铜层，使得催化剂层不被暴露，留下薄的铜层。 然后，通过去除任何突出的绝缘材料来研磨和调平基板表面。 此后，在衬底的表面上沉积另一个铜层，包括填充材料上的表面区域，并被电路化以形成布线图案。 由于当衬底上的铜层变薄时催化剂层不暴露，所以可以获得精细的布线图案，而不会导致布线导体随后的剥离或空气的夹带。

公开(公告)号：US06351194B2

公开(公告)日：2002-02-26

申请号：US09106086

申请日：1998-06-29

Applicant: Yoshiro Takahashi ,  Kei Nakakuki ,  Satoshi Itaya ,  Kayo Hamano

Inventor： Yoshiro Takahashi ,  Kei Nakakuki ,  Satoshi Itaya ,  Kayo Hamano

IPC: H03H972

CPC classification number: H03H9/725 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/73253 ,  H01L2924/01019 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03H9/0576 ,  H03H9/6433 ,  H03H9/72 ,  H05K1/0201 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/0298 ,  H05K1/112 ,  H05K3/429 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/10371 ,  H05K2201/10674 ,  H05K2203/1394

Abstract: An electronic component having a multi-layered printed circuit board made of an organic material, a plurality of electronic components mounted in a face-down position on the multi-layered printed circuit board, a metal cover for covering the plurality of electronic components remaining a space or a cavity between the top surface of the printed circuit board and the inner surface of the metal cover having a flange surrounding the outskirts of the metal cover to be adhered to the top surface of the multi-layered printed circuit board, and a heat conductive member packed between the bottom surface of the electronic components, wherein the multi-layered printed circuit board has at least one through-hole vertically penetrating the multi-layered printed circuit board at a location corresponding to the flange and is lined by a metal film, and the multi-layered printed circuit board has a heat conductive layer arranged along the rear surface of the multi-layered printed circuit board, the heat conductive layer being connected to a metal lining of the through-hole.

Abstract translation: 一种具有由有机材料制成的多层印刷电路板的电子部件，多层印刷电路板上以面朝下的方式安装的多个电子部件，用于覆盖剩余的多个电子部件的金属盖 空间或印刷电路板的顶表面和金属盖的内表面之间的空腔，其具有围绕金属盖的外围的凸缘以粘附到多层印刷电路板的顶表面，并且热量 导电构件，其被包装在电子部件的底表面之间，其中所述多层印刷电路板具有至少一个在与所述凸缘相对应的位置处垂直贯穿所述多层印刷电路板的通孔，并且由金属膜 ，并且多层印刷电路板具有沿着多层印刷电路板的后表面布置的导热层，hea t导电层与通孔的金属衬里连接。

公开(公告)号：US06348844B1

公开(公告)日：2002-02-19

申请号：US09594771

申请日：2000-06-16

Applicant: Björn Albinsson ,  Thomas Harju

Inventor： Björn Albinsson ,  Thomas Harju

IPC: H01P508

CPC classification number: H05K1/024 ,  H01P5/08 ,  H05K1/0298 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09536 ,  H05K2201/09845

Abstract: The present invention relates to an arrangement in multilayer printed circuit boards, with the aim of improving matching in transitions between symmetric striplines (3) and asymmetric striplines (4). The requirement of a coverpad (6) for contact between the via (5) and the asymmetric stripline (4) for dimension reasons among other things, results in matching problems. In order to avoid this problem, the earth plane (7, 10) nearest the transition is moved away in the proximity of the via (5).

Abstract translation: 本发明涉及多层印刷电路板中的布置，目的是改善对称带状线（3）和非对称带状线（4）之间的转换中的匹配。 由于维度上的其他原因，通孔（5）和非对称带状线（4）之间的接触的盖板（6）的要求导致匹配问题。 为了避免这个问题，最接近过渡部分的接地平面（7,10）在通孔（5）附近被移开。

公开(公告)号：US06344371B2

公开(公告)日：2002-02-05

申请号：US09136201

申请日：1998-08-19

Applicant: Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

Inventor： Paul J. Fischer ,  Robin E. Gorrell ,  Mark F. Sylvester

IPC: H01L2144

CPC classification number: H01L23/49827 ,  H01L2924/0002 ,  H05K3/323 ,  H05K3/427 ,  H05K3/429 ,  H05K3/445 ,  H05K3/4608 ,  H05K3/4614 ,  H05K3/4641 ,  H05K2201/0116 ,  H05K2201/015 ,  H05K2201/09536 ,  Y10T428/24917 ,  Y10T428/249958 ,  Y10T442/3415 ,  H01L2924/00

Abstract: A dimensionally stable core for use in high density chip packages is provided. The stable core is a metal core, preferably copper, having clearances formed therein. Dielectric layers are provided concurrently on top and bottom surfaces of the metal core. Metal cap layers are provided concurrently on top surfaces of the dielectric layers. Blind or through vias are then drilled through the metal cap layers and extend into the dielectric layers and clearances formed in the metal core. If an isolated metal core is provided then the vias do not extend through the clearances in the copper core. The stable core reduces material movement of the substrate and achieves uniform shrinkage from substrate to substrate during lamination processing of the chip packages. This allows each substrate to perform the same. Additionally, a plurality of chip packages having the dimensionally stable core can be bonded together to obtain a high density chip package.

Abstract translation: 提供了用于高密度芯片封装的尺寸稳定的芯。 稳定的芯是具有在其中形成间隙的金属芯，优选铜。 电介质层同时设置在金属芯的顶表面和底表面上。 金属盖层同时设置在电介质层的顶表面上。 然后通过金属盖层钻出盲孔或通孔，并延伸到形成在金属芯中的电介质层和间隙中。 如果提供隔离的金属芯，则通孔不延伸穿过铜芯中的间隙。 稳定的芯材可降低基板的材料运动，并在芯片封装的层压处理期间实现从基板到基板的均匀收缩。 这允许每个基板执行相同的操作。 此外，具有尺寸稳定的芯的多个芯片封装可以结合在一起以获得高密度芯片封装。

公开(公告)号：US20010023780A1

公开(公告)日：2001-09-27

申请号：US09812817

申请日：2001-03-21

Applicant: NEC CORPORATION

Inventor： Shigeru Mori

IPC: H05K001/03

CPC classification number: H05K1/0271 ,  H05K3/4602 ,  H05K3/4623 ,  H05K3/4626 ,  H05K3/4688 ,  H05K2201/0278 ,  H05K2201/068 ,  H05K2201/09536 ,  H05K2201/0959

Abstract: A printed wiring board is formed by a printed wiring substrate having a plurality of a wiring layer, and a thermal expansion buffering sheet having lower coefficient of thermal expansion than that of said printed wiring substrate, which is integrally laminated on a surface of the printed wiring substrate.

Abstract translation: 印刷布线板由具有多个布线层的印刷布线基板和热膨胀系数比所述印刷布线基板的热膨胀系数低的热膨胀缓冲片形成，该片材整体层压在印刷布线的表面上 基质。

公开(公告)号：US06266874B1

公开(公告)日：2001-07-31

申请号：US09118735

申请日：1998-07-17

Applicant: Thomas H. DiStefano ,  John W. Smith ,  Konstantine N. Karavakis ,  Zlata Kovac ,  Joseph Fjelstad

Inventor： Thomas H. DiStefano ,  John W. Smith ,  Konstantine N. Karavakis ,  Zlata Kovac ,  Joseph Fjelstad

IPC: H05K310

CPC classification number: H01R13/2414 ,  H01R12/714 ,  H05K1/0272 ,  H05K1/036 ,  H05K1/056 ,  H05K1/116 ,  H05K3/0032 ,  H05K3/445 ,  H05K3/462 ,  H05K3/4623 ,  H05K3/4641 ,  H05K2201/0382 ,  H05K2201/09536 ,  H05K2201/09554 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/10378 ,  H05K2203/0554 ,  H05K2203/0582 ,  H05K2203/135 ,  H05K2203/308 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method of making a microelectronic component by providing a conductive element, providing a resist at selected locations on said conductive element and electrophoretically depositing an uncured dielectric material on the conductive element, wherein the uncured material will be deposited on the conductive element except at locations covered by the resist. The deposited material is cured to form a dielectric layer and the resist is removed so that the dielectric layer has openings extending to the conductive element at locations the locations which were covered by the resist.

Abstract translation: 一种通过提供导电元件制造微电子元件的方法，在所述导电元件上的选定位置提供抗蚀剂并在导电元件上电泳沉积未固化的介电材料，其中未固化的材料将沉积在导电元件上，除了覆盖的位置 由抗蚀剂。 固化沉积的材料以形成电介质层，并且去除抗蚀剂，使得电介质层具有在被抗蚀剂覆盖的位置的位置处延伸到导电元件的开口。