中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

863 records (took 0.031 seconds)

    FABRICATION PROCESS FOR A SYMMETRICAL MEMS ACCELEROMETER
    13.
    发明申请
    FABRICATION PROCESS FOR A SYMMETRICAL MEMS ACCELEROMETER 审中-公开

    公开(公告)号：US20170336437A1

    公开(公告)日：2017-11-23

    申请号：US15659963

    申请日：2017-07-26

    Applicant: Chinese Academy of Sciences Institute of Geology and Geophysics

    Inventor： Lianzhong YU ,  Chen Sun ,  Leiyang Yi

    IPC: G01P15/125 ,  G01P15/08

    CPC classification number: B81C3/001 ,  B81B2201/0235 ,  B81B2203/051 ,  B81C1/00134 ,  B81C1/0019 ,  B81C1/00269 ,  B81C1/00357 ,  B81C1/00396 ,  B81C1/00531 ,  B81C1/00539 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/014 ,  B81C2201/019 ,  G01P15/125 ,  G01P2015/0814

    Abstract: A process for fabricating a symmetrical MEMS accelerometer. A pair of half parts is fabricated by, for each half part: (i) forming a plurality of resilient beams, first connecting parts, second connecting parts, and a plurality of comb structures, by etching a plurality of holes on a bottom surface of a first silicon wafer; (ii) etching a plurality of hollowed parts on a top surface of a second silicon wafer; (iii) forming a silicon dioxide layer on the top and bottom surface of the second silicon wafer; (iv) bonding the bottom surface of the first silicon wafer with the top surface of the second silicon wafer; (v) depositing a layer of silicon nitride on the bottom surface of the second silicon wafer, and removing parts of the silicon nitride layer and silicon dioxide layer on the bottom surface of the second silicon wafer; (vii) deep etching the exposed parts of the bottom surface of the second silicon wafer to the silicon dioxide layer located on the top surface of the second silicon wafer, and reducing the thickness of the first silicon wafer; and (viii) removing the silicon nitride layer, and etching the silicon dioxide to form the mass. The two half parts are then bonded along their bottom surface. The device is deep etched to form a movable accelerometer. A bottom cap is fabricated by hollowing out the corresponding area, and depositing metal as electrodes. The accelerometer is bonded with the bottom cap. Metal is deposited on the first silicon wafer to form electrodes.

    COMPOSITE CAVITY AND FORMING METHOD THEREOF
    16.
    发明申请
    COMPOSITE CAVITY AND FORMING METHOD THEREOF 审中-公开
    复合孔及其形成方法

    公开(公告)号：US20170044006A1

    公开(公告)日：2017-02-16

    申请号：US15305799

    申请日：2014-11-05

    Applicant: ADVANCED SEMICONDUCTOR MANUFACTURING CO. LTD

    Inventor： Yuanjun Xu ,  Yilin Yan ,  Weijia Xue

    IPC: B81B7/02 ,  B81C1/00

    CPC classification number: B81B7/02 ,  B81B2201/0257 ,  B81B2203/0127 ,  B81B2203/0315 ,  B81C1/00158 ,  B81C1/00396 ,  B81C2201/0132 ,  B81C2201/0133 ,  B81C2201/019 ,  B81C2201/0198 ,  B81C2201/053

    Abstract: There is provided a method for forming a composite cavity and a composite cavity formed using the method. The method comprises the following steps: providing a silicon substrate (101); forming an oxide layer on the front side thereof; patterning the oxide layer to form one or more grooves (103), the position of the groove (103) corresponding to the position of small cavity (109) to be formed; providing a bonding wafer (104), which is bonded to the patterned oxide layer to form one or more closed micro-cavity structures (105) between the silicon substrate (101) and the bonding wafer (104); forming a protective film (106) over the bonding wafer (104) and forming a masking layer (107) on the back side of the silicon substrate (101); patterning the masking layer (107), the pattern of the masking layer (107) corresponding to the position of a large cavity (108) to be formed; using the masking layer (107) as a mask, etching the silicon substrate (101) from the back side until the oxide layer at the front side thereof to form the large cavity (108) in the silicon substrate (101); and using the masking layer (107) and the oxide layer as a mask, etching the bonding wafer (104) from the back side through the silicon substrate (101) until the protective film (106) thereover to form one or more small cavities (109) in the bonding wafer (104). The uniformity of thickness of the semiconductor medium layer where the small cavity (109) in the composite cavity is located is well controlled by the present invention.

    Abstract translation: 提供了使用该方法形成复合腔和复合腔的方法。 该方法包括以下步骤：提供硅衬底（101）; 在其前侧形成氧化物层; 图案化氧化物层以形成一个或多个凹槽（103），凹槽（103）的位置对应于待形成的小空腔（109）的位置; 提供接合晶片（104），其接合到所述图案化氧化物层以在所述硅衬底（101）和所述接合晶片（104）之间形成一个或多个闭合微腔结构（105）; 在所述接合晶片（104）上形成保护膜（106），并在所述硅衬底（101）的背侧上形成掩模层（107）; 图案化掩模层（107），对应于待形成的大空腔（108）的位置的掩模层（107）的图案; 使用掩模层（107）作为掩模，从背面蚀刻硅衬底（101）直到其前侧的氧化物层在硅衬底（101）中形成大空腔（108）; 并且使用所述掩模层（107）和所述氧化物层作为掩模，通过所述硅衬底（101）从所述背面蚀刻所述接合晶片（104）直到所述保护膜（106）在其上形成一个或多个小空腔 109）。 复合空腔中的小空腔（109）所在的半导体介质层的厚度均匀性由本发明很好地控制。

Patent Agency Ranking