公开(公告)号：US20170244184A1

公开(公告)日：2017-08-24

申请号：US15422978

申请日：2017-02-02

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H05K1/11 ,  H01R13/405 ,  H01R13/05

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.

公开(公告)号：US20170150605A1

公开(公告)日：2017-05-25

申请号：US15116042

申请日：2015-05-13

Applicant: Sony Corporation

Inventor： Takashi NAGAI ,  Hiroyuki KUMAGAI

IPC: H05K1/18 ,  H01M10/42 ,  H01M10/0525 ,  H05K1/11 ,  H05K3/34

CPC classification number: H05K1/181 ,  H01M10/0525 ,  H01M10/425 ,  H05K1/111 ,  H05K3/28 ,  H05K3/34 ,  H05K3/3442 ,  H05K3/3452 ,  H05K2201/09472 ,  H05K2201/09663 ,  H05K2201/0969 ,  H05K2201/09745 ,  H05K2201/099 ,  H05K2201/09909 ,  H05K2203/0588 ,  Y02P70/611

Abstract: An electronic apparatus is provided including a substrate, a conductive land formed on a surface of the substrate, an electronic component including an electrode, at least one insulating protrusion formed on the land in an overlapping region between the land and the electrode in plan view, and a solder that bonds the electronic component to the land, the solder being formed between the electrode and the land in the overlapping region in a normal direction to the surface of the substrate.

公开(公告)号：US09627360B2

公开(公告)日：2017-04-18

申请号：US15262304

申请日：2016-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC: G01R31/00 ,  H01L25/065 ,  H05K1/11 ,  H05K1/18 ,  H01L21/66 ,  H01L23/00 ,  G11C5/06

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US09596765B2

公开(公告)日：2017-03-14

申请号：US14426364

申请日：2012-09-11

Applicant: Akira Yamaki ,  Tatsuya Kikuchi ,  Mitsuaki Toda

Inventor： Akira Yamaki ,  Tatsuya Kikuchi ,  Mitsuaki Toda

IPC: H05K3/30 ,  H05K3/00 ,  H05K1/18 ,  H05K3/46 ,  H01L23/00 ,  C25D7/06 ,  H05K1/09 ,  H05K3/40 ,  H01L23/544 ,  H01L21/683 ,  H05K1/02 ,  H01L21/56

CPC classification number: H05K3/0008 ,  C25D7/0607 ,  H01L21/568 ,  H01L21/6835 ,  H01L23/544 ,  H01L24/19 ,  H01L24/27 ,  H01L24/29 ,  H01L24/32 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2221/68359 ,  H01L2223/54426 ,  H01L2223/54486 ,  H01L2224/04105 ,  H01L2224/2741 ,  H01L2224/27436 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32245 ,  H01L2224/82039 ,  H01L2224/82132 ,  H01L2224/83005 ,  H01L2224/83132 ,  H01L2224/8314 ,  H01L2224/83192 ,  H01L2224/92144 ,  H01L2924/12042 ,  H01L2924/14 ,  H05K1/0269 ,  H05K1/09 ,  H05K1/185 ,  H05K1/188 ,  H05K3/305 ,  H05K3/4007 ,  H05K3/403 ,  H05K3/4038 ,  H05K3/4602 ,  H05K3/4655 ,  H05K3/4658 ,  H05K3/4661 ,  H05K3/4682 ,  H05K2201/0209 ,  H05K2201/0293 ,  H05K2201/09063 ,  H05K2201/09472 ,  H05K2201/09918 ,  H05K2203/0353 ,  H05K2203/0361 ,  H05K2203/063 ,  H01L2924/00

Abstract: A manufacturing method for a component incorporated substrate according to the present invention includes positioning an electronic component with reference to a mark formed on a copper layer, the mark consisting of a material less easily etched than copper by a copper etching agent used for etching of copper, after mounting the electronic component on the copper layer with an adhesive layer interposed therebetween, embedding the electronic component and the mark in an insulating substrate, thereafter, etching and removing a part of the copper layer to form a window for exposing the mark, forming an LVH reaching a terminal of the electronic component with reference to the exposed mark, electrically connecting the terminal and the copper layer via a conduction via formed by applying copper plating to the LVH, and, thereafter, forming the copper layer into a wiring pattern.

Abstract translation: 根据本发明的用于组件的基片的制造方法包括：根据形成在铜层上的标记来定位电子部件，该标记由铜蚀刻剂（铜蚀刻剂）蚀刻铜不易蚀刻的材料构成 在将电子部件粘附在铜层上之后，将电子部件和标记嵌入绝缘基板后，将铜层的一部分进行蚀刻除去，形成露出标记的窗口，形成 参照曝光标记的LVH到达电子部件的端子，经由通过将电镀施加到LVH而形成的导通孔将端子和铜层电连接，然后将铜层形成布线图案。

公开(公告)号：US20170019993A1

公开(公告)日：2017-01-19

申请号：US14798384

申请日：2015-07-13

Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.

Inventor： Li-Chuan TSAI ,  Chih-Cheng LEE

IPC: H05K1/11 ,  H05K1/18 ,  H05K3/40 ,  H05K3/00 ,  H05K3/22 ,  H05K1/02 ,  H05K3/36

CPC classification number: H01L23/49838 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/17 ,  H01L2224/16227 ,  H01L2924/15153 ,  H01L2924/15313 ,  H01L2924/19105 ,  H05K1/0266 ,  H05K1/0298 ,  H05K1/111 ,  H05K1/115 ,  H05K1/181 ,  H05K1/183 ,  H05K3/0017 ,  H05K3/0026 ,  H05K3/0047 ,  H05K3/22 ,  H05K3/36 ,  H05K3/40 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/0158 ,  H05K2201/09472 ,  H05K2201/09527 ,  H05K2201/10204 ,  H05K2203/166 ,  Y02P70/611

Abstract: The present disclosure relates to a semiconductor substrate, a semiconductor module and a method for manufacturing the same. The semiconductor substrate includes a first dielectric structure, a second dielectric structure, a first patterned conductive layer and a second patterned conductive layer. The first dielectric structure has a first surface and a second surface opposite the first surface. The second dielectric structure has a third surface and a fourth surface opposite the third surface, where the fourth surface is adjacent to the first surface. The second dielectric structure defines a through hole extending from the third surface to the fourth surface. A cavity is defined by the through hole and the first dielectric structure. The first patterned conductive layer is disposed on the first surface of the first dielectric structure. The second patterned conductive layer is disposed on the second surface of the first dielectric structure.

Abstract translation: 本公开涉及半导体衬底，半导体模块及其制造方法。 半导体衬底包括第一电介质结构，第二电介质结构，第一图案化导电层和第二图案化导电层。 第一电介质结构具有与第一表面相对的第一表面和第二表面。 第二电介质结构具有与第三表面相对的第三表面和第四表面，其中第四表面与第一表面相邻。 第二电介质结构限定了从第三表面延伸到第四表面的通孔。 空腔由通孔和第一电介质结构限定。 第一图案化导电层设置在第一电介质结构的第一表面上。 第二图案化导电层设置在第一介电结构的第二表面上。

公开(公告)号：US20160315042A1

公开(公告)日：2016-10-27

申请号：US15007557

申请日：2016-01-27

Applicant: Samsung Electro-Mechanics Co., Ltd.

Inventor： Kyoung-Ro YOON ,  Hyun-Kyung PARK

IPC: H01L23/498 ,  H01L21/683 ,  H01L21/288 ,  H01L21/48

CPC classification number: H01L21/288 ,  H01L21/4857 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2221/68345 ,  H01L2224/16225 ,  H05K1/113 ,  H05K1/141 ,  H05K2201/049 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/10242 ,  H05K2201/10378

Abstract: Disclosed is a printed circuit board including an insulating layer, a circuit layer formed on a lower surface of the insulating layer, and a metal post contacting the circuit layer and extending from the lower surface to an upper surface of the insulating layer. The printed circuit board is able to prevent shorts while components are mounted by forming a metal post to have a secured height tolerance to connect with a die and to be in a caved shape into the board.

Abstract translation: 公开了一种印刷电路板，其包括绝缘层，形成在绝缘层的下表面上的电路层和接触电路层并从绝缘层的下表面延伸到上表面的金属柱。 印刷电路板能够通过形成金属柱来安装元件以防止短路，以具有固定的高度公差以与模具连接并且将其形成为凹陷形状。

公开(公告)号：US09449716B2

公开(公告)日：2016-09-20

申请号：US14719321

申请日：2015-05-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Guk Han ,  Seok-Joon Moon ,  Beom-jun Jin

IPC: G01R31/00 ,  G11C29/12 ,  H01L23/538 ,  H01L25/18 ,  H05K1/02 ,  G01R31/28 ,  H01L21/66 ,  G11C5/02 ,  H01L23/498 ,  G11C5/06 ,  G11C29/04 ,  H05K1/18 ,  G11C29/56 ,  H01L25/065 ,  H05K1/11 ,  H05K3/28 ,  H05K3/32 ,  H01L23/00 ,  H05K3/00 ,  H05K3/24

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US20160242277A1

公开(公告)日：2016-08-18

申请号：US15041925

申请日：2016-02-11

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae-Ean LEE ,  Jee-Soo MOK ,  Young-Gwan KO ,  Soon-Oh JUNG ,  Kyung-Hwan KO ,  Yong-Ho BAEK

IPC: H05K1/02 ,  H05K3/46 ,  H05K3/16 ,  H05K1/11

CPC classification number: H05K3/4697 ,  H05K1/113 ,  H05K3/282 ,  H05K3/4007 ,  H05K3/4644 ,  H05K2201/09472

Abstract: A printed circuit board and method of manufacturing the same are provided. The printed circuit board includes a first substrate including a first insulation layer and a first circuit layer including a bonding pad, the bonding pad disposed on the first insulation layer, a second substrate disposed on the first substrate and having a cavity exposing the bonding pad to an outside, and a dam disposed between the bonding pad and an inner wall of the cavity.

Abstract translation: 提供一种印刷电路板及其制造方法。 印刷电路板包括：第一基板，包括第一绝缘层和第一电路层，第一电路层包括接合焊盘，所述接合焊盘设置在所述第一绝缘层上;第二基板，设置在所述第一基板上，并且具有将所述接合焊盘暴露于 外部和设置在接合焊盘和空腔的内壁之间的坝。

公开(公告)号：US20160165720A1

公开(公告)日：2016-06-09

申请号：US15046696

申请日：2016-02-18

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Kosuke NISHINO ,  Kuniaki YOSUI

IPC: H05K1/02 ,  H05K1/03 ,  H05K3/00 ,  H05K1/14

CPC classification number: H05K1/0298 ,  H05K1/0296 ,  H05K1/0313 ,  H05K1/144 ,  H05K3/0058 ,  H05K3/4632 ,  H05K2201/09472

Abstract: In a method for manufacturing a multilayer substrate, conductive patterns to define mounting electrodes are formed on a principal surface of a first base layer, and conductive patterns are formed on principal surfaces of other base layers. The base layers are stacked such that the principal surface of the first base layer is the outermost surface. The stacked base layers are laminated by pressing an elastic body to the side of the first base layer to form a multilayer body. In the multilayer body, the conductive patterns are arranged such that the proportion of the conductive patterns in regions overlapping the conductive patterns on the first base layer as viewed in the stacking direction is lower than that in a region surrounding the regions overlapping the conductive patterns.

Abstract translation: 在制造多层基板的方法中，在第一基底层的主表面上形成用于限定安装电极的导电图案，并且在其它基底层的主表面上形成导电图案。 基底层被堆叠成使得第一基底层的主表面是最外表面。 通过将弹性体按压到第一基底层的侧面来层叠堆叠的基底层，以形成多层体。 在多层体中，导电图案被布置成使得在层叠方向上观察时，与第一基底层上的导电图案重叠的区域中的导电图案的比例低于覆盖与导电图案重叠的区域的区域中的导电图案的比例。

公开(公告)号：US20160150635A1

公开(公告)日：2016-05-26

申请号：US14927888

申请日：2015-10-30

Applicant: HongQiSheng Precision Electronics (QinHuanDao) Co., Ltd. ,  FuKui Precision Component (Shenzhen) Co., Ltd. ,  Zhen Ding Technology Co., Ltd.

Inventor： XIAN-QIN HU ,  YAN-LU LI ,  LI-BO ZHANG

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/09 ,  H05K3/42

CPC classification number: H05K1/0251 ,  H05K1/115 ,  H05K3/4015 ,  H05K3/4623 ,  H05K3/4688 ,  H05K2201/09063 ,  H05K2201/09472 ,  H05K2201/09845 ,  H05K2201/10303 ,  H05K2203/061

Abstract: The flexible printed circuit board includes a base layer, a first circuit layer and a second circuit layer, the first circuit and the second circuit layer formed on both sides of the base layer; conducting holes extending through the base layer and the first copper layer, the conducting holes include annular copper ring embedded in the first circuit layer. A height difference between a surface of the annular copper ring and a surface of the first circuit layer is in a range from 0 to 3 micrometers. A method for manufacturing the flexible printed circuit board is also provided.

Abstract translation: 柔性印刷电路板包括基层，第一电路层和第二电路层，第一电路和第二电路层形成在基层的两侧; 导电孔延伸穿过基层和第一铜层，导电孔包括嵌入第一电路层的环形铜环。 环形铜环的表面与第一电路层的表面之间的高度差在0至3微米的范围内。 还提供了一种用于制造柔性印刷电路板的方法。