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    Above motherboard interposer with quarter wavelength electrical paths
    11.
    发明授权
    Above motherboard interposer with quarter wavelength electrical paths 有权
    在主板上插入四分之一波长的电路径

    公开(公告)号：US09357648B2

    公开(公告)日：2016-05-31

    申请号：US14790302

    申请日：2015-07-02

    Applicant: MORGAN / WEISS TECHNOLOGIES INC.

    Inventor： Morgan Johnson ,  Frederick G. Weiss

    IPC: H05K1/11 ,  G06F1/32 ,  H05K1/02 ,  H01L23/32 ,  H05K1/14 ,  H05K1/18

    CPC classification number: G06F13/16 ,  G06F1/32 ,  G06F13/4068 ,  G11C5/04 ,  H01L23/32 ,  H01L23/49838 ,  H01L23/4985 ,  H01L2924/0002 ,  H05K1/0237 ,  H05K1/0243 ,  H05K1/0296 ,  H05K1/111 ,  H05K1/115 ,  H05K1/141 ,  H05K1/147 ,  H05K1/181 ,  H05K1/189 ,  H05K2201/095 ,  H05K2201/10159 ,  H05K2201/10189 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10522 ,  Y02D10/151 ,  Y10T29/4913 ,  H01L2924/00

    Abstract: A multi-layer interposer substrate includes multiple layers of single interposer substrates. Each single interposer substrate has a first array of interposer interconnects, each interposer interconnect in the first array of interposer interconnects corresponding to interconnects in an array of processor interconnects, a second array of interposer interconnects, each interposer interconnect in the second array of the interposer interconnects corresponding to an array of circuit interconnects on a circuit substrate, and at least one conductive trace in the interposer substrate in connection with at least one interconnect in the first array of interposer interconnects. The conductive trace has a parallel portion parallel to the interposer substrate such that no electrical connection exists between the interconnect and a corresponding one of the interposer interconnects in the second array of interposer interconnects. An array of connections for a peripheral circuit on each single interposer is connected to the at least one conductive trace.

    Abstract translation: 多层插入器衬底包括多层单个插入器衬底。 每个单个插入器衬底具有第一内插器互连阵列，每个插入器互连在插入器互连的第一阵列中对应于处理器互连阵列中的互连，插入器互连的第二阵列，插入器互连的第二阵列中的每个插入器互连 对应于电路基板上的电路互连阵列，以及与插入器互连的第一阵列中的至少一个互连相关联的插入器基板中的至少一个导电迹线。 导电迹线具有平行于插入器基板的平行部分，使得互连和第二插入器互连阵列中的相应的一个插入器互连之间不存在电连接。 每个单个插入器上的外围电路的连接阵列连接到至少一个导电迹线。

    MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE
    12.
    发明申请
    MANUFACTURING A SEMICONDUCTOR PACKAGE INCLUDING AN EMBEDDED CIRCUIT COMPONENT WITHIN A SUPPORT STRUCTURE OF THE PACKAGE 有权
    在包装的支持结构中制造包括嵌入式电路组件的半导体封装

    公开(公告)号：US20130122658A1

    公开(公告)日：2013-05-16

    申请号：US13296707

    申请日：2011-11-15

    Applicant: Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

    Inventor： Jovica Savic ,  Zhiping Yang ,  Jie Xue ,  Li Li

    IPC: H01L21/56

    CPC classification number: H05K1/183 ,  H01L23/24 ,  H01L23/3107 ,  H01L23/49838 ,  H01L2224/16225 ,  H01L2924/0002 ,  H05K1/115 ,  H05K1/181 ,  H05K2201/095 ,  H05K2201/10492 ,  H05K2201/10507 ,  H01L2924/00

    Abstract: A method and apparatus are provided in which a cavity is formed in a support structure, the support structure being operable to support a semiconductor device, disposing at least a portion of a circuit element in the cavity in the support structure, filling the cavity in the support structure with an electrically non-conductive filling material so as to at least partially surround the circuit element with the non-conductive filling material, and electrically connecting the semiconductor device to the circuit element. In an example embodiment, the circuit element is operable to substantially block direct current that is output by the semiconductor device or another semiconductor device.

    Abstract translation: 提供了一种方法和装置，其中空腔形成在支撑结构中，支撑结构可操作以支撑半导体器件，将电路元件的至少一部分设置在支撑结构中的空腔中，将空腔填充在 支撑结构，其具有不导电的填充材料，以至少部分地围绕电路元件与非导电填充材料，并将半导体器件电连接到电路元件。 在示例性实施例中，电路元件可操作以基本上阻挡由半导体器件或另一半导体器件输出的直流电流。

    CIRCUIT STRUCTURE
    13.
    发明公开
    CIRCUIT STRUCTURE 审中-公开

    公开(公告)号：US20240306295A1

    公开(公告)日：2024-09-12

    申请号：US18119268

    申请日：2023-03-08

    Applicant: Advanced Semiconductor Engineering, Inc.

    Inventor： Wen-Long LU

    IPC: H05K1/11 ,  H01L21/768 ,  H05K1/02 ,  H05K3/40

    CPC classification number: H05K1/115 ,  H01L21/76871 ,  H05K1/024 ,  H05K3/40 ,  H05K2201/09145 ,  H05K2201/09218 ,  H05K2201/095 ,  H05K2203/0502

    Abstract: A circuit structure includes a low-density conductive structure, a high-density conductive structure and a plurality of traces. The high-density conductive structure is disposed over the low-density conductive structure, and defines an opening extending from a top surface of the high-density conductive structure to a bottom surface of the high-density conductive structure. The opening exposes a first pad of the low-density conductive structure and a second pad of the low-density conductive structure. The second pad is spaced apart from the first pad. The traces extend from the top surface of the high-density conductive structure into the opening. The traces include a first trace connecting to the first pad of the low-density conductive structure and a second trace connecting to the second pad of the low-density conductive structure.

    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD FOR THE SAME
    15.
    发明公开
    PRINTED CIRCUIT BOARD AND MANUFACTURING METHOD FOR THE SAME 审中-公开

    公开(公告)号：US20240057267A1

    公开(公告)日：2024-02-15

    申请号：US18093584

    申请日：2023-01-05

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Soo Yun KIM ,  Jung Soo KIM

    IPC: H05K3/40 ,  H05K1/11 ,  H05K3/46

    CPC classification number: H05K3/4038 ,  H05K1/115 ,  H05K3/46 ,  H05K2201/095

    Abstract: Disclosed is a printed circuit board and a manufacturing method for manufacturing the same, the printed circuit board including: a first insulating layer; a through-hole penetrating through the first insulating layer; a via conductor layer disposed in the through-hole, and having first and second groove portions recessed inwardly of the through-hole from an upper surface and a lower surface of the first insulating layer, respectively; a cavity penetrating through at least a portion of the first insulating layer; an electronic component disposed in the cavity; and a second insulating layer covering at least a portion of the first insulating layer, and disposed in at least a portion of each of the through-hole and the cavity.

    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE
    16.
    发明公开
    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20240055745A1

    公开(公告)日：2024-02-15

    申请号：US18223075

    申请日：2023-07-18

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Nobuo IKEMOTO ,  Masanori OKAMOTO

    IPC: H01P3/08 ,  H05K1/14 ,  H01P3/12 ,  H05K1/09 ,  H05K1/02 ,  H05K1/05

    CPC classification number: H01P3/088 ,  H05K1/144 ,  H01P3/12 ,  H05K1/09 ,  H05K1/028 ,  H05K1/05 ,  H05K2201/095

    Abstract: A multilayer substrate includes a multilayer body including resin layers stacked in a Z-axis direction, a signal conductor layer, and one or more through conductors passing through a first resin layer in the Z-axis direction. A first main surface of the first resin layer includes one or more hollow portions not in contact with the signal conductor layer and overlapping the signal conductor layer when viewed in the Z-axis direction. Each of the one or more hollow portions and the one or more through conductors includes a tapered region in which each of a cross-sectional area of the one or more hollow portions orthogonal to the Z-axis direction and a cross-sectional area of the one or more through conductors orthogonal to the Z-axis direction increases toward the first main surface. The tapered region is in contact with the first main surface of the first resin layer.

    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE
    18.
    发明公开
    MULTILAYER SUBSTRATE AND ELECTRONIC DEVICE 审中-公开

    公开(公告)号：US20230299453A1

    公开(公告)日：2023-09-21

    申请号：US18201212

    申请日：2023-05-24

    Applicant: Murata Manufacturing Co., Ltd.

    Inventor： Nobuo IKEMOTO ,  Kentarou KAWABE

    IPC: H01P3/08 ,  H05K1/02 ,  H05K1/14

    CPC classification number: H01P3/088 ,  H01P3/082 ,  H05K1/028 ,  H05K1/144 ,  H05K2201/095

    Abstract: A multilayer substrate includes layers stacked on each other in an up-down direction of a multilayer body. The layers include a first spacer, a first ground conductive layer above the first spacer, and a signal conductive layer that overlaps the first ground conductive layer and is located below the first spacer. First through-holes pass through the first spacer and are arranged along a first direction. A distance between centroids of first through-holes adjacent to each other in the first direction is uniform or substantially uniform. Sets of first through-holes are provided in the first spacer. Sets of first through-holes are arranged along a second direction. A distance between centroids of first through-holes adjacent to each other in the second direction is uniform or substantially uniform. At least one first through-hole is a first hollow through-hole overlapping the signal conductive layer.

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