公开(公告)号：US20230189444A1

公开(公告)日：2023-06-15

申请号：US17955683

申请日：2022-09-29

Applicant: Zhuhai ACCESS Semiconductor Co., Ltd

Inventor： Xianming CHEN ,  Lei FENG ,  Gao HUANG ,  Benxia HUANG ,  Yejie HONG

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K3/00 ,  H05K3/46 ,  H05K3/42

CPC classification number: H05K1/186 ,  H05K1/113 ,  H05K1/0366 ,  H05K3/0035 ,  H05K3/4661 ,  H05K3/429 ,  H05K2201/032 ,  H05K2201/09509 ,  H05K2201/0129 ,  H05K2201/0166 ,  H05K2203/061 ,  H05K2203/308

Abstract: A method for manufacturing a structure for embedding and packaging multiple devices by layer includes preparing a polymer supporting frame, mounting a first device in a first device placement mouth frame to form a first packaging layer, forming a first circuit layer and a second circuit layer, forming a second conductive copper pillar layer and a second sacrificial copper pillar layer, forming a second insulating layer on the first circuit layer, and forming a third insulating layer on the second circuit layer, forming a second device placement mouth frame vertically overlapped with the first device placement mouth frame, mounting a second device and a third device in the second device placement mouth frame to form a second packaging layer, forming a third circuit layer on the second insulating layer. A terminal of the second device and a terminal of the third device are respectively communicated with the third circuit layer.

公开(公告)号：US20230189431A1

公开(公告)日：2023-06-15

申请号：US17925059

申请日：2021-05-13

Applicant: LG INNOTEK CO., LTD.

Inventor： Won Suk JUNG

IPC: H05K1/02 ,  H05K1/11

CPC classification number: H05K1/0225 ,  H05K1/116 ,  H05K2201/096 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A circuit board according to an embodiment includes an insulating layer; a second outer circuit pattern disposed on an upper surface of the insulating layer; and a via disposed in the insulating layer and connected to the second outer circuit pattern; wherein the second outer circuit pattern includes: a first pattern embedded in the insulating layer and having a first width; and a second pattern protruding on the upper surface of the insulating layer, having a second width greater than the first width, and connected to the first pattern through the via.

公开(公告)号：US20230156918A1

公开(公告)日：2023-05-18

申请号：US17853933

申请日：2022-06-30

Applicant: Unimicron Technology Corp.

Inventor： Shih-Lian Cheng

IPC: H05K1/11 ,  H05K1/02

CPC classification number: H05K1/116 ,  H05K1/0222 ,  H05K2201/09509 ,  H05K2201/0195

Abstract: A circuit board structure includes a substrate, a third dielectric layer, a fourth dielectric layer, a first external circuit layer, a second external circuit layer, a conductive through hole, a first annular retaining wall, and a second annular retaining wall. The conductive through hole penetrates through the third dielectric layer, a second dielectric layer, and the fourth dielectric layer. The conductive through hole is electrically connected to the first external circuit layer and the second external circuit layer. The first annular retaining wall is disposed in the third dielectric layer, surrounds the conductive through hole, and is electrically connected to the first external circuit layer and the first inner circuit layer. The second annular retaining wall is disposed in the fourth dielectric layer, surrounds the conductive through hole, and connects to the second external circuit layer and the second inner circuit layer electrically.

公开(公告)号：US20180242456A1

公开(公告)日：2018-08-23

申请号：US15748100

申请日：2016-08-10

Applicant: Schweizer Electronic AG

Inventor： Thomas GOTTWALD ,  Christian RÖSSLE

IPC: H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11 ,  H01Q1/38

CPC classification number: H05K1/186 ,  H01Q1/38 ,  H05K1/024 ,  H05K1/0243 ,  H05K1/115 ,  H05K1/181 ,  H05K1/185 ,  H05K3/4614 ,  H05K3/4617 ,  H05K3/462 ,  H05K3/4694 ,  H05K3/4697 ,  H05K2201/015 ,  H05K2201/09127 ,  H05K2201/09509 ,  H05K2201/09936 ,  H05K2201/10098 ,  H05K2201/10378 ,  H05K2203/0285 ,  H05K2203/063 ,  H05K2203/166

Abstract: Method for producing a conductor structural element with a layer sequence having an internal layer substrate, including the steps: providing a rigid carrier having an underside and a top side; defining a cut-out section on the rigid carrier; applying at least one electrically insulating layer with a recess in such a way that the cut-out section is exposed; placing an internal layer substrate above the cut-out section with formation of a cavity between the rigid carrier and the internal layer substrate; aligning and fixing the internal layer substrate relative to the rigid carrier; laminating the layer construction prepared in this manner such that resin material of the at least one electrically insulating layer liquefies and encloses the internal layer substrate with the cavity being left free; producing a cut-out by cutting the cut-out section out of the rigid carrier from the outer underside of the rigid carrier.

公开(公告)号：US20180242448A1

公开(公告)日：2018-08-23

申请号：US15896166

申请日：2018-02-14

Applicant: ARISAWA MFG. CO., LTD.

Inventor： Kazuo YOSHIKAWA ,  Makoto TAI ,  Nobuyuki IWANO ,  Takayuki MAYAMA

IPC: H05K1/03 ,  H05K3/00 ,  C08L53/00 ,  C08K3/36 ,  C09J153/00 ,  B32B7/12 ,  B32B15/08 ,  B32B15/20

CPC classification number: H05K1/036 ,  B32B7/12 ,  B32B15/08 ,  B32B15/20 ,  B32B2250/02 ,  B32B2250/05 ,  B32B2255/10 ,  B32B2255/26 ,  B32B2379/08 ,  B32B2457/08 ,  C08K3/36 ,  C08K2003/2227 ,  C08L53/005 ,  C09J7/10 ,  C09J7/387 ,  C09J153/005 ,  C09J2201/622 ,  C09J2203/326 ,  C09J2205/102 ,  C09J2453/00 ,  H05K1/024 ,  H05K1/0373 ,  H05K1/0393 ,  H05K1/09 ,  H05K3/0035 ,  H05K3/0038 ,  H05K3/022 ,  H05K3/386 ,  H05K2201/0112 ,  H05K2201/0133 ,  H05K2201/0154 ,  H05K2201/0209 ,  H05K2201/09509 ,  H05K2201/2063 ,  H05K2203/107

Abstract: The present invention provides a resin composition comprising a specific styrene polymer, a specific inorganic filler, and a curing agent, wherein the styrene polymer is a specific acid-modified styrene polymer, and the resin composition satisfies specific conditions in the form of a film having a thickness of 25 μm.

公开(公告)号：US09963797B2

公开(公告)日：2018-05-08

申请号：US15031317

申请日：2014-10-09

Applicant: Atotech Deutschland GmbH

Inventor： Andreas Macioβek ,  Olivier Mann ,  Pamela Cebulla

IPC: C25D5/18 ,  C25D7/12 ,  C25D3/38 ,  C25D5/02 ,  C25D5/56 ,  C25D17/00 ,  C25D17/10 ,  C25D21/18

CPC classification number: C25D5/02 ,  C25D3/38 ,  C25D5/022 ,  C25D5/18 ,  C25D5/56 ,  C25D7/123 ,  C25D17/001 ,  C25D17/10 ,  C25D21/18 ,  H05K2201/09509

Abstract: The method for copper electroplating according to the present invention comprises an aqueous acidic copper plating bath containing a leveler additive which forms copper trenches having a cross-sectional round shape under direct current plating conditions, and at least one reverse current pulse cycle consisting of one forward current pulse and one reverse current pulse wherein the fraction of the reverse charge to the forward charge applied to the substrate in said at least one current pulse cycle ranges between 0.1 to 5%. The method is particularly suitable for simultaneously filling blind micro vias and plating trenches with a rectangular cross-sectional shape.

公开(公告)号：US09958744B2

公开(公告)日：2018-05-01

申请号：US15356058

申请日：2016-11-18

Applicant: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

Inventor： Jihun Choi ,  Jae-Eun Pi

IPC: H01L31/00 ,  G02F1/1345 ,  H01L27/12 ,  H01L23/00

CPC classification number: G02F1/13458 ,  H01L23/498 ,  H01L24/05 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L27/124 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/06102 ,  H01L2224/1403 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/1703 ,  H01L2224/81447 ,  H05K1/113 ,  H05K2201/094 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/10659 ,  H05K2201/10674 ,  H01L2924/00014

Abstract: Provided is display panel including a substrate including a pixel area and a pad area; and a first conductive line and a second conductive line stacked on the substrate, wherein the first conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area and the second conductive line includes a first part disposed on the pixel area and a second part disposed on the pad area. The first part of the first conductive line and the first part of the second conductive line are parallel to each other and the second part of the first conductive line and the second part of the second conductive line are overlapped vertically.

公开(公告)号：US09936588B2

公开(公告)日：2018-04-03

申请号：US13655135

申请日：2012-10-18

Applicant: Lenovo Enterprise Solutions (Singapore) Pte. Ltd.

Inventor： Mark E. Andresen ,  Virginia Ott

IPC: H05K3/30 ,  H05K3/00

CPC classification number: H05K3/308 ,  H05K3/0047 ,  H05K2201/044 ,  H05K2201/09509 ,  H05K2201/10303 ,  H05K2201/10545 ,  H05K2201/10871 ,  H05K2203/0207 ,  Y10T29/4913 ,  Y10T29/49144 ,  Y10T29/49147 ,  Y10T29/49165

Abstract: A printed circuit board having one or more holes that are controllably drilled to extend into the printed circuit board substrate to a predetermined depth intermediate first and second faces. A mechanical locating pin is received into each of the one or more holes to mechanically align a first component for electronically interfacing with the printed circuit board substrate. A second component is installed on the second face directly opposite of the one or more holes such that the second component is in electronic communication with conductive traces or interconnects formed on the second face directly opposite of the hole.

公开(公告)号：US09832866B2

公开(公告)日：2017-11-28

申请号：US15196857

申请日：2016-06-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Seok-Hwan Ahn ,  Mi-Sun Hwang ,  Young-Gwan Ko ,  Jong-Seok Bae ,  Myung-Sam Kang

IPC: H05K1/09 ,  H05K1/02 ,  H05K3/00 ,  H05K3/46 ,  H05K1/11 ,  H05K3/40 ,  H05K3/12

CPC classification number: H05K1/0298 ,  H05K1/0271 ,  H05K1/09 ,  H05K1/115 ,  H05K1/165 ,  H05K3/007 ,  H05K3/0076 ,  H05K3/12 ,  H05K3/4007 ,  H05K3/4617 ,  H05K3/4623 ,  H05K2201/09136 ,  H05K2201/09509 ,  H05K2201/09563 ,  H05K2201/09672 ,  H05K2203/043

Abstract: A multilayered substrate includes unit substrates laminated in a direction of thickness thereof, and the unit substrates include a photosensitive insulating layer, a conductive pattern disposed in the photosensitive insulating layer, and a bump penetrating into the photosensitive insulating layer and providing an interlayer connection to the conductive pattern.

公开(公告)号：US20170244184A1

公开(公告)日：2017-08-24

申请号：US15422978

申请日：2017-02-02

Applicant: MERCURY SYSTEMS, INC.

Inventor： Darryl J. MCKENNEY ,  Absu METHRATTA ,  Erica OUELLETTE

IPC: H01R12/71 ,  H05K1/02 ,  H05K1/11 ,  H01R13/405 ,  H01R13/05

CPC classification number: H01R12/58 ,  H01R4/028 ,  H01R12/00 ,  H01R12/526 ,  H01R12/714 ,  H01R12/716 ,  H01R13/05 ,  H01R13/405 ,  H01R13/652 ,  H05K1/0213 ,  H05K1/0237 ,  H05K1/0298 ,  H05K1/11 ,  H05K1/111 ,  H05K1/112 ,  H05K1/115 ,  H05K1/181 ,  H05K1/184 ,  H05K3/308 ,  H05K3/34 ,  H05K3/3421 ,  H05K3/42 ,  H05K3/421 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09545 ,  H05K2201/09827 ,  H05K2201/10098 ,  H05K2201/10189 ,  H05K2201/10295 ,  H05K2201/1078 ,  H05K2201/10803 ,  H05K2201/10871 ,  H05K2201/10878 ,  H05K2201/10901 ,  H05K2203/0455 ,  Y02P70/611

Abstract: According to exemplary embodiments, a tapered surface interconnect is formed on a printed circuit board (PCB). A compliant pin of an electrical connector may be coupled to the tapered surface interconnect and soldered thereto. The surface interconnect may be formed by drilling through one or more layers of the PCB. The depth of the surface interconnect may be shorter than a height or a thickness of the PCB. The surface interconnect may have a tapered side wall to allow for a better fit with a tapered compliant pin. The inclination of the side wall of the surface interconnect may be linear or concave. The intersection between the tapered sidewall and the bottom of the surface interconnect may be rounded to minimize pin insertion issues and may allow for easier solder flux evacuation. The compliant pin may be soldered into place upon being coupled to the tapered surface interconnect.