公开(公告)号：US07235886B1

公开(公告)日：2007-06-26

申请号：US10023819

申请日：2001-12-21

Applicant: Biju Chandran ,  Carlos A. Gonzalez

Inventor： Biju Chandran ,  Carlos A. Gonzalez

IPC: H01L23/488

CPC classification number: H01L24/81 ,  H01L2224/13147 ,  H01L2224/16237 ,  H01L2224/81048 ,  H01L2224/81097 ,  H01L2224/81801 ,  H01L2924/00013 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674 ,  H05K2201/2036 ,  H05K2203/0475 ,  Y02P70/613 ,  Y10T29/49144 ,  H01L2224/29099

Abstract: A chip-join process to reduce elongation mismatch between the adherents involves thermally expanding each of a coefficient of thermal expansion mismatched semiconductor chip and substrate a substantially equal amount from their room temperature state in a direction along surfaces thereof to be joined by soldering. The thermally expanded semiconductor chip and substrate are then soldered to one another forming a plurality of soldered joints, and then cooled to room temperature. The process enables elongation mismatch from soldering to be reduced to less than half that expected based up cooling the substrate and semiconductor chip from the solder solidification temperature following soldering, thereby reducing post soldering residual stress, residual plastic deformation in the soldered joints, residual plastic deformation in the substrate, and semiconductor chip warpage.

Abstract translation: 用于减少粘附剂之间的伸长失配的芯片连接工艺涉及将热膨胀不匹配的半导体芯片和衬底的每个热膨胀从其室温状态沿与其通过焊接接合的表面的方向基本相等的量。 然后将热膨胀的半导体芯片和基板彼此焊接形成多个焊接接头，然后冷却至室温。 该工艺使钎焊时的伸长失配降低到小于焊接后基板和半导体芯片从焊料凝固温度下降的预期的一半，从而减少焊后残余应力，焊接接头残余塑性变形，残余塑性变形 在基板上，半导体芯片翘曲。

公开(公告)号：US20070115640A1

公开(公告)日：2007-05-24

申请号：US11599586

申请日：2006-11-15

Applicant: Akihiro Shibasaki ,  Katsumi Inukai ,  Tasuku Sugimoto

Inventor： Akihiro Shibasaki ,  Katsumi Inukai ,  Tasuku Sugimoto

IPC: H05K7/20

CPC classification number: B41J29/02 ,  H05K1/0259 ,  H05K2201/0367 ,  H05K2201/10022

Abstract: An electronic apparatus that includes: a circuit board; a switch attached to the circuit board; an electronic part mounted on the circuit board; a wiring pattern extending between the switch and the electronic part; and a protrusion protruding from a surface of the wiring pattern, the protrusion being disposed adjacent to the switch on the circuit board and overlapping the wiring pattern.

Abstract translation: 一种电子设备，包括：电路板; 连接到电路板的开关; 安装在电路板上的电子部件; 在开关和电子部件之间延伸的布线图案; 以及从所述布线图案的表面突出的突起，所述突起与所述电路板上的所述开关相邻设置并且与所述布线图案重叠。

公开(公告)号：US20070114674A1

公开(公告)日：2007-05-24

申请号：US11285001

申请日：2005-11-22

Applicant: Matthew Brown

Inventor： Matthew Brown

IPC: H01L23/48

CPC classification number: H05K1/111 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/13 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/19041 ,  H05K3/243 ,  H05K3/3452 ,  H05K3/3457 ,  H05K2201/0367 ,  H05K2201/09736 ,  H05K2201/099 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Disclosed herein is a solder pad interface for a solder joint on a substrate. The solder pad interface includes a soldermask defined (SMD) interface between a solder pad (202) and the substrate, and a non-soldermask defined (NSMD) interface between the solder pad and the solder joint. The SMD interface can include a layer of insulating material (208) configured as an overlaid stencil with apertures through which the NSMD interface of the solder pad is substantially accessible. The SMD interface can include a soldermask (210) configured to cover an outer portion (212) of the solder pad. The NSMD interface includes a raised central portion (214) of the solder pad having a top. The layer of insulating material can be substantially flush with the top of the raised central portion. The raised central portion can provide the NSMD interface between the solder pad and the solder joint.

Abstract translation: 这里公开了一种用于衬底上的焊接接头的焊盘界面。 焊盘接口包括在焊盘（202）和衬底之间限定的（SMD）接口和在焊料焊盘和焊接接头之间的非焊接掩模界定（NSMD）界面。 SMD接口可以包括被配置为具有孔的覆盖模板的绝缘材料层（208），焊料垫的NSMD界面基本可接近。 SMD接口可以包括被配置为覆盖焊盘的外部部分（212）的焊接掩模（210）。 NSMD接口包括具有顶部的焊盘的凸起的中心部分（214）。 绝缘材料层可以与凸起的中心部分的顶部基本齐平。 凸起的中心部分可以在焊盘和焊点之间提供NSMD接口。

公开(公告)号：US20070114653A1

公开(公告)日：2007-05-24

申请号：US11657280

申请日：2007-01-24

Applicant: Osamu Shiono ,  Takao Ishikawa ,  Takashi Namekawa ,  Yasutaka Suzuki ,  Takashi Naito ,  Hiroki Yamamoto ,  Daigoro Kamoto ,  Ken Takahashi ,  Tadanori Segawa ,  Toshiya Sato ,  Takao Miwa ,  Shigehisa Motowaki

Inventor： Osamu Shiono ,  Takao Ishikawa ,  Takashi Namekawa ,  Yasutaka Suzuki ,  Takashi Naito ,  Hiroki Yamamoto ,  Daigoro Kamoto ,  Ken Takahashi ,  Tadanori Segawa ,  Toshiya Sato ,  Takao Miwa ,  Shigehisa Motowaki

IPC: H01L23/12

CPC classification number: H05K3/4061 ,  H01L21/486 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49883 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/16 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/49175 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01063 ,  H01L2924/01067 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/19011 ,  H01L2924/19041 ,  H01L2924/19104 ,  H01L2924/19105 ,  H01L2924/30107 ,  H05K1/0306 ,  H05K1/113 ,  H05K3/426 ,  H05K2201/0116 ,  H05K2201/0367 ,  H05K2201/09563 ,  H05K2201/09581 ,  H05K2201/09827 ,  H05K2201/09981 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A wiring glass substrate includes a glass substrate formed of glass and having a plurality of holes formed at predetermined positions, bumps so formed as to be connected to a conductive material filling the holes and wirings formed on a surface opposite to a surface having the bumps formed thereon and electrically connecting a plurality of connection terminals arranged in intervals different from intervals of the holes to the conductive material. The shape of the conductive material is porous and porous electrodes are bonded to the inner wall surfaces of the holes by an anchor effect to increase the strength of the glass substrate.

公开(公告)号：US20070103180A1

公开(公告)日：2007-05-10

申请号：US11588707

申请日：2006-10-27

Applicant: Alan Wood ,  Tim Corbett

Inventor： Alan Wood ,  Tim Corbett

IPC: G01R31/02

CPC classification number: H01L24/80 ,  G01R1/0466 ,  G01R1/0483 ,  G01R1/0491 ,  G01R1/0735 ,  G01R3/00 ,  G01R31/2831 ,  G01R31/2855 ,  G01R31/2863 ,  G01R31/2867 ,  G01R31/2886 ,  G01R31/2889 ,  G01R31/2893 ,  H01L22/20 ,  H01L22/22 ,  H01L23/13 ,  H01L2224/16145 ,  H01L2225/06562 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15151 ,  H05K3/0058 ,  H05K3/0067 ,  H05K3/4007 ,  H05K3/423 ,  H05K2201/0133 ,  H05K2201/0347 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2203/0307 ,  H05K2203/0723

Abstract: A reusable burn-in/test fixture for testing unsingulated dice on a semiconductor wafer consisting of two halves. The first half of the test fixture is a wafer cavity plate for receiving the wafer, and the second half establishes electrical communication between the wafer and electrical testing equipment. A rigid substrate has conductors thereon which establish electrical contact with the wafer. The test fixture need not be opened until the burn-in and electrical testing are completed. After burn-in stress and electrical testing, it is possible to establish interconnection between the single die or separate and package dice into discrete parts, arrays or clusters, either as singulated parts or as arrays.

公开(公告)号：US07211735B2

公开(公告)日：2007-05-01

申请号：US10028624

申请日：2001-12-20

Applicant: Yutaka Kaneda

Inventor： Yutaka Kaneda

IPC: H05K1/00

CPC classification number: H05K3/0002 ,  H05K1/0393 ,  H05K3/002 ,  H05K3/0082 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/4614 ,  H05K3/4635 ,  H05K2201/0166 ,  H05K2201/0367 ,  H05K2203/056 ,  H05K2203/0733 ,  H05K2203/1545 ,  Y10S428/901 ,  Y10T29/49128 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T428/24917

Abstract: A process for manufacturing a multilayer flexible wiring board, which allows individual layers of wiring boards to be precisely positioned and to be readily stacked. A mask for exposure is prepared in which a plurality of pattern holes corresponding to individual layers of wiring boards of a multilayer flexible wiring board are arranged in the direction perpendicular to the transporting direction P of substrate. This mask for exposure is used to form a plurality of wiring patterns corresponding to individual layers of wiring boards of a multilayer flexible wiring board on the same sheet-like substrate.

Abstract translation: 一种制造多层柔性布线板的方法，其允许各层布线板精确定位并容易堆叠。 制备用于曝光的掩模，其中与垂直于基板的传送方向P的方向布置与多层柔性布线板的布线板的各层相对应的多个图案孔。 该曝光用掩模用于形成与同一片状基板上的多层柔性布线基板的各层布线基板对应的多个布线图案。

公开(公告)号：US20070085203A1

公开(公告)日：2007-04-19

申请号：US11563355

申请日：2006-11-27

Applicant: Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

Inventor： Takashi Kariya ,  Toshiki Furutani ,  Hirofumi Goto ,  Shin-ichiro Iwanaga

IPC: H01L23/48

CPC classification number: H01L23/49822 ,  H01L23/49811 ,  H01L23/49816 ,  H01L2224/16 ,  H01L2224/16235 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01068 ,  H01L2924/01078 ,  H01L2924/01079 ,  H05K1/0271 ,  H05K1/0373 ,  H05K1/115 ,  H05K3/28 ,  H05K3/4007 ,  H05K3/4602 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/068 ,  H05K2201/10674

Abstract: A multilayer printed wiring board is equipped with a core board 20, a build-up layer 30 formed on the core board 20 so as to have a conductor pattern 32 on the upper surface thereof, a low-elasticity layer 40 formed on the build-up layer 30, lands 52 that are provided on the upper surface of the low-elasticity layer 40 and connected to an IC chip 70 via solder bumps 66, and conductor posts 50 that penetrate through the low-elasticity layer 40 and electrically connect the lands 52 to the conductor pattern 32. The low-elasticity layer 40 is formed of resin composition containing epoxy resin, phenol resin, cross-linked rubber particles and a hardening catalyst.

Abstract translation: 多层印刷电路板配备有芯板20，形成在芯板20上的积层30，以在其上表面具有导体图案32，形成在构建层20上的低弹性层40， 上层30，设置在低弹性层40的上表面上并通过焊锡凸块66连接到IC芯片70的焊盘52以及穿过低弹性层40并导电连接焊盘的导体柱50 52到导体图案32。 低弹性层40由含有环氧树脂，酚醛树脂，交联橡胶粒子和硬化催化剂的树脂组合物形成。

公开(公告)号：US07205661B2

公开(公告)日：2007-04-17

申请号：US11268884

申请日：2005-11-08

Applicant: James M. Wark ,  Salman Akram

Inventor： James M. Wark ,  Salman Akram

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L24/10 ,  G01R1/06738 ,  H01L22/34 ,  H01L23/49811 ,  H01L23/49816 ,  H01L24/12 ,  H01L24/13 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05551 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/05555 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15787 ,  H05K3/325 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/0373 ,  H05K2201/10734 ,  Y10T29/49147 ,  Y10T29/49155 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A bumped semiconductor device contact structure is disclosed including at least one non-planar contact pad having a plurality of projections extending therefrom for contacting at least one solder ball of a bumped integrated circuit (IC) device, such as a bumped die and a bumped packaged IC device. The projections are arranged to make electrical contact with the solder balls of a bumped IC device without substantially deforming the solder ball. Accordingly, reflow of solder balls to reform the solder balls is not necessary with the contact pad of the present invention. Such a contact pad may be provided on various testing equipment such as probes and the like and may be used for both temporary and permanent connections. Also disclosed is an improved method of forming the contact pads by etching and deposition.

Abstract translation: 公开了凸起的半导体器件接触结构，其包括至少一个非平面接触焊盘，其具有从其延伸的多个突起，用于接触凸起的集成电路（IC）器件的至少一个焊球，例如凸起的裸片和凸起的封装 IC设备。 突起被布置成与凸起的IC器件的焊球电接触，而不会使焊球基本上变形。 因此，本发明的接触焊盘不需要焊球的回流以重新形成焊球。 这样的接触垫可以设置在诸如探针等的各种测试设备上，并且可以用于临时和永久连接。 还公开了通过蚀刻和沉积形成接触焊盘的改进方法。

公开(公告)号：US20070080439A1

公开(公告)日：2007-04-12

申请号：US11542261

申请日：2006-10-04

Applicant: Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

Inventor： Katsumi Kikuchi ,  Shintaro Yamamichi ,  Yoichiro Kurita ,  Koji Soejima

IPC: H01L23/02

CPC classification number: H01L25/0657 ,  H01L21/6835 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2221/68345 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/1532 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K3/20 ,  H05K3/28 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/09881 ,  H05K2201/0989 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A wiring board comprising a first surface on which a first electrode is disposed and a second surface on which a second electrode is disposed; at least a single insulation layer and at least a single wiring layer; and one or a plurality of mounted semiconductor elements, wherein the second electrode disposed on the second surface is embedded in the insulation layer, the surface on the opposite side of the exposed surface on the second surface side of the second electrode is connected to the wiring layer, and all or part of the side surface of the second electrode does not make contact with the insulation layer.

Abstract translation: 一种布线板，包括：第一表面，其上设置有第一电极;第二表面，其上设置有第二电极; 至少单个绝缘层和至少一个布线层; 以及一个或多个安装的半导体元件，其中设置在第二表面上的第二电极嵌入在绝缘层中，在第二电极的第二表面侧上的暴露表面的相对侧上的表面连接到布线 层，并且第二电极的全部或部分侧面不与绝缘层接触。

公开(公告)号：US20070057022A1

公开(公告)日：2007-03-15

申请号：US11499358

申请日：2006-08-04

Applicant: Keiichi Mogami ,  Hiroshi Asami

Inventor： Keiichi Mogami ,  Hiroshi Asami

IPC: A47J36/02

CPC classification number: H05K3/3436 ,  H01G2/065 ,  H01L21/563 ,  H01L23/498 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/81 ,  H01L2224/03505 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/29111 ,  H01L2224/2919 ,  H01L2224/73203 ,  H01L2224/81011 ,  H01L2224/81193 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/83191 ,  H01L2224/83856 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01022 ,  H01L2924/01025 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/1579 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/351 ,  H05K1/111 ,  H05K3/3489 ,  H05K3/4007 ,  H05K2201/0367 ,  H05K2201/10674 ,  H05K2201/10977 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2224/1134

Abstract: A component mounting method configured to mount on a wiring board a surface-mount electronic component that has an electrode terminal on a bonding surface, the method including the steps of preparing the electronic component having a solder layer that covers the electrode terminal, and a resin layer that is provided on the solder layer and has a flux function preparing the wiring board having a projection conductor that is formed on a mounting surface and is to be bonded to the electrode terminal and mounting the electronic component on the wiring board, and implementing reflow of the solder layer so that the projection conductor penetrates the resin layer.

Abstract translation: 一种部件安装方法，其被配置为在接线板上安装在接合面上具有电极端子的表面安装电子部件，所述方法包括准备具有覆盖所述电极端子的焊料层的电子部件和树脂 层，其具有制备布线基板的通量函数，该布线基板具有形成在安装面上并与电极端子接合并将电子部件安装在布线基板上的突起导体，并实现回流焊 的焊料层，使得突起导体穿过树脂层。