公开(公告)号：US09030011B2

公开(公告)日：2015-05-12

申请号：US13959567

申请日：2013-08-05

Applicant: Xintec Inc.

Inventor： Chao-Yen Lin ,  Yi-Hang Lin

IPC: H01L23/00 ,  H01L21/56 ,  H01L21/683 ,  H01L23/31 ,  H01L23/525 ,  H01L29/06

CPC classification number: H01L24/05 ,  G06K9/0004 ,  H01L21/561 ,  H01L21/6835 ,  H01L23/3121 ,  H01L23/525 ,  H01L24/08 ,  H01L24/13 ,  H01L24/48 ,  H01L29/06 ,  H01L29/0657 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381 ,  H01L2224/02371 ,  H01L2224/02375 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05548 ,  H01L2224/05558 ,  H01L2224/06165 ,  H01L2224/06167 ,  H01L2224/0801 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/24226 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73253 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/10156 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15788 ,  H01L2924/3701 ,  H05K1/181 ,  H05K2201/09418 ,  H05K2201/09445 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/03

Abstract: An embodiment of the invention provides a chip package which includes: a carrier substrate; a semiconductor substrate having an upper surface and a lower surface, disposed overlying the carrier substrate; a device region or sensing region located on the upper surface of the semiconductor substrate; a conducting pad located on the upper surface of the semiconductor substrate; a conducting layer electrically connected to the conducting pad and extending from the upper surface of the semiconductor substrate to a sidewall of the semiconductor substrate; and an insulating layer located between the conducting layer and the semiconductor substrate.

Abstract translation: 本发明的实施例提供了一种芯片封装，其包括：载体基板; 具有上表面和下表面的半导体衬底，设置在载体衬底上; 位于所述半导体衬底的上表面上的器件区域或感测区域; 导电焊盘，位于所述半导体衬底的上表面上; 导电层，电连接到导电焊盘并从半导体衬底的上表面延伸到半导体衬底的侧壁; 以及位于导电层和半导体衬底之间的绝缘层。

公开(公告)号：US08901686B2

公开(公告)日：2014-12-02

申请号：US13303337

申请日：2011-11-23

Applicant: Satoru Hiramoto ,  Koichiro Matsumoto ,  Yoshiyuki Kono ,  Akitoshi Mizutani

Inventor： Satoru Hiramoto ,  Koichiro Matsumoto ,  Yoshiyuki Kono ,  Akitoshi Mizutani

IPC: H01L29/82 ,  H05K1/11 ,  H05K1/18 ,  H05K3/34

CPC classification number: H05K1/111 ,  H05K1/189 ,  H05K3/3421 ,  H05K3/3442 ,  H05K2201/09418 ,  Y02P70/611

Abstract: A mounting structure for mounting a chip type electric element on a flexible board includes: the flexible board having a first land, on which a first lead terminal of another electric element is soldered; and the chip type electric element having a long side. A whole of the long side of the chip type electric element faces a long side of the first land. A length of the long side of the first land is defined as IA, and a distance between one long side of the first land and one long side of the chip type electric element is defined as IB, the one long side of the first land facing the chip type electric element but opposite to the one long side of the chip type electric element. The length of IA is equal to or larger than the distance of IB.

Abstract translation: 用于将芯片型电气元件安装在柔性基板上的安装结构包括：柔性板，其具有第一焊盘，焊接另一个电气元件的第一引线端子; 芯片型电气元件具有长边。 芯片式电气元件的整个长边面对第一焊盘的长边。 第一焊盘的长边的长度被定义为IA，并且第一焊盘的一个长边与芯片式电气元件的一个长边之间的距离被定义为IB，第一焊盘面的一个长边 芯片型电气元件，但与芯片型电气元件的一个长边相对。 IA的长度等于或大于IB的距离。

公开(公告)号：US20140168909A1

公开(公告)日：2014-06-19

申请号：US13719506

申请日：2012-12-19

Applicant: Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

Inventor： Tieyu Zheng ,  Jin A. Zhao ,  Ru Han ,  Min Pei

IPC: H05K1/18 ,  H05K1/03

CPC classification number: H05K3/3452 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/09418 ,  H05K2201/0969 ,  H05K2201/0989 ,  H05K2201/099 ,  Y02P70/611

Abstract: Attachment structures for electrically coupling a microelectronic package to a microelectronic board/interposer including joint pads formed on the microelectronic board/interposer which provide a gap between respective openings in a solder resist layer of the microelectronic substrate and each of the joint pads. Such attachment structures may reduce or substantially eliminate contact between a solder interconnect and a solder resist layer of the microelectronic board/interposer, which may, in turn, reduce or substantially eliminate the potential of crack initiation and propagation at contact areas between the solder interconnect and a solder resist layer of the microelectronic board/interposer due to stresses induced by a mismatch of thermal expansion between the microelectronic package and the microelectronic board/interposer during thermal cycling. Further, the connection area between the pad and outside circuitry may be maximized, so that the impact to electrical performance due to the pad design may be minimized.

Abstract translation: 用于将微电子封装电耦合到包括形成在微电子板/插入件上的接合焊盘的微电子板/插入件的附接结构，其提供微电子衬底的阻焊层中的各个开口之间的间隙以及每个接合焊盘。 这种附接结构可以减少或基本上消除微电子板/插入件的焊料互连和阻焊层之间的接触，这又可以减少或基本消除在焊料互连和焊接互连之间的接触区域处的裂纹发生和传播的可能性 由于在热循环期间微电子封装和微电子板/插入件之间的热膨胀不匹配引起的应力，微电子板/插入件的阻焊层。 此外，焊盘和外部电路之间的连接区域可以最大化，使得由于焊盘设计而对电性能的影响可能被最小化。

公开(公告)号：US08607446B2

公开(公告)日：2013-12-17

申请号：US13182364

申请日：2011-07-13

Applicant: Kenji Fukuda

Inventor： Kenji Fukuda

IPC: H01R9/00 ,  H05K3/00

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L24/17 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A method of manufacturing an electronic component, which includes arranging a plurality of first electrode pads on a first substrate, and a plurality of second electrode pads on a second substrate, so that the first and second electrode pads correspond to each other. The method further includes forming a plurality of solder bumps on the second electrode pads and putting the first substrate over the second substrate. The first and second substrates are shifted in parallel to each other, in a horizontal direction, while the solder bumps are melting, so that the solder bumps are stretched in a slant direction to cause the solder bumps to be solidified into hourglass-shapes.

Abstract translation: 一种制造电子部件的方法，其包括在第一基板上布置多个第一电极焊盘，在第二基板上布置多个第二电极焊盘，使得第一和第二电极焊盘彼此对应。 该方法还包括在第二电极焊盘上形成多个焊料凸块并将第一衬底放置在第二衬底上。 第一基板和第二基板在水平方向上彼此平行地移动，同时焊料凸点熔化，使得焊料凸块沿倾斜方向拉伸以使焊料凸块固化成沙漏形状。

公开(公告)号：US20130313007A1

公开(公告)日：2013-11-28

申请号：US13901398

申请日：2013-05-23

Applicant: Massachusetts Institute of Technology

Inventor： Dmitry Tolpin ,  James H. Kelly ,  Roger M. Maurais

IPC: H05K1/11 ,  H05K3/30

CPC classification number: H05K3/301 ,  H01L2224/16225 ,  H01L2924/10253 ,  H01L2924/351 ,  H01L2924/381 ,  H05K1/111 ,  H05K1/18 ,  H05K1/181 ,  H05K3/30 ,  H05K3/303 ,  H05K3/3436 ,  H05K2201/068 ,  H05K2201/094 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2201/10242 ,  Y02P70/611 ,  Y10T29/4913 ,  Y10T29/49133 ,  H01L2924/00

Abstract: Reliability is improved for the mechanical electrical connection formed between a grid array device, such as a pin grid array device (PGA) or a column grid array device (CGA), and a substrate such as a printed circuit board (PCB). Between adjacent PCB pads, a spacing pattern increases toward the periphery of the CGA, creating a misalignment between pads and columns. As part of the assembly method, columns align with the pads, resulting in column tilt that increases from the center to the periphery of the CGA. An advantage of this tilt is that it reduces the amount of contractions and expansions of columns during thermal cycling, thereby increasing the projected life of CGA. Another advantage of the method is that it reduces shear stress, further increasing the projected life of the CGA.

Abstract translation: 对于诸如针阵列阵列器件（PGA）或列格栅阵列器件（CGA）的栅格阵列器件和诸如印刷电路板（PCB）的衬底之间形成的机械电连接，可靠性得到改善。 在相邻的PCB焊盘之间，间隔图案朝向CGA的周边增加，导致焊盘和柱之间的未对准。 作为组装方法的一部分，列与焊盘对准，导致从CGA的中心到外围增加的列倾斜。 这种倾斜的一个优点是在热循环期间减少了柱的收缩量和膨胀量，从而增加了CGA的预计使用寿命。 该方法的另一个优点是降低了剪切应力，进一步提高了CGA的寿命。

公开(公告)号：US20130037945A1

公开(公告)日：2013-02-14

申请号：US13596322

申请日：2012-08-28

Applicant: Min Jae Lee ,  You Shin Chung ,  Hoon Jung

Inventor： Min Jae Lee ,  You Shin Chung ,  Hoon Jung

IPC: H05K1/02 ,  H01L23/48

CPC classification number: H01L24/17 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/14 ,  H01L24/16 ,  H01L2224/0401 ,  H01L2224/05553 ,  H01L2224/05567 ,  H01L2224/13014 ,  H01L2224/13022 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1412 ,  H01L2224/14133 ,  H01L2224/16105 ,  H01L2224/16238 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/81203 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2924/00014 ,  H05K3/303 ,  H05K3/3452 ,  H05K2201/09418 ,  H05K2201/10674 ,  H05K2201/10977 ,  H05K2203/166 ,  H01L2924/014 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: Provided is a semiconductor device in which misalignment between a semiconductor die and a substrate (e.g., a circuit board) can be prevented or substantially reduced when the semiconductor die is attached to the circuit board. In a non-limiting example, the semiconductor device includes: a semiconductor die comprising at least one bump; and a circuit board comprising at least one circuit pattern to which the bump is electrically connected. In a non-limiting example, the circuit board comprises: an insulation layer comprising a center region and peripheral regions around the center region; a plurality of center circuit patterns formed in the center region of the insulation layer; and a plurality of peripheral circuit patterns formed in the peripheral regions of the insulation layer. The center circuit patterns may be formed wider than the peripheral circuit patterns, formed in a zigzag pattern, and/or may be formed in a crossed shape.

Abstract translation: 提供一种半导体器件，其中当半导体管芯附接到电路板时，可以防止或显着减小半导体管芯和衬底（例如电路板）之间的偏移。 在非限制性示例中，半导体器件包括：包括至少一个凸块的半导体管芯; 以及电路板，其包括至少一个电路图案，所述凸块电连接到所述电路图案。 在非限制性示例中，电路板包括：绝缘层，包括中心区域和围绕中心区域的周边区域; 形成在所述绝缘层的中心区域中的多个中心电路图案; 以及形成在绝缘层的周边区域中的多个外围电路图案。 中心电路图案可以形成为比以Z字形图案形成的外围电路图形更宽，和/或可以形成为交叉形状。

公开(公告)号：US20110269306A1

公开(公告)日：2011-11-03

申请号：US13182364

申请日：2011-07-13

Applicant: KENJI FUKUDA

Inventor： KENJI FUKUDA

IPC: H01L21/283

CPC classification number: B23K1/0016 ,  B23K2101/40 ,  H01L24/17 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05147 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/351 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09427 ,  H05K2203/0465 ,  Y02P70/613 ,  Y10T29/49149 ,  Y10T29/49151 ,  Y10T29/49155 ,  Y10T29/49204 ,  H01L2924/00 ,  H01L2924/00014

Abstract: An electronic component includes a plurality of first electrode pads arranged on a first substrate, a plurality of second electrode pads arranged at positions corresponding to the first electrode pads on a second substrate and a plurality of solder bumps which join together the first electrode pads and the second electrode pads. Here, the first substrate is located over the second substrate so that the first electrode pads and the second electrode pads are at positions which are shifted from opposite positions where the first electrode pads opposite to the second electrode pads, and at least a part of the solder bumps are solidified into hourglass-shaped.

Abstract translation: 电子部件包括布置在第一基板上的多个第一电极焊盘，布置在与第二基板上的第一电极焊盘相对应的位置处的多个第二电极焊盘以及将第一电极焊盘连接在一起的多个焊料凸块 第二电极垫。 这里，第一衬底位于第二衬底上，使得第一电极焊盘和第二电极焊盘处于与第二电极焊盘相对的第一电极焊盘的相对位置偏移的位置，并且至少一部分 焊料凸块固化成沙漏形。

公开(公告)号：US07994428B2

公开(公告)日：2011-08-09

申请号：US12335449

申请日：2008-12-15

Applicant: Kuo-Ching Tsai ,  Chang-fu Lin Chang

Inventor： Kuo-Ching Tsai ,  Chang-fu Lin Chang

IPC: H01L23/48 ,  H05K1/03

CPC classification number: H05K1/111 ,  H01L24/13 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05568 ,  H01L2224/13011 ,  H01L2224/13016 ,  H01L2224/161 ,  H01L2224/81193 ,  H01L2224/81194 ,  H01L2224/81801 ,  H01L2924/0002 ,  H01L2924/01033 ,  H05K3/3436 ,  H05K2201/09418 ,  H05K2201/09745 ,  H05K2201/10674 ,  Y02P70/611 ,  Y02P70/613 ,  H01L2224/05552

Abstract: An electronic carrier board for a chip to be mounted thereon is provided, which includes a body and a plurality of solder pads. The solder pads have carrying surfaces for carrying the chip thereon through conductive bumps. The carrying surfaces of at least two solder pads are oppositely inclined with respect to each other, thereby preventing the conductive bumps mounted on the carrying surfaces from displacement and thereby further preventing two adjacent conductive bumps subject to displacement from coming into short-circuit contact.

Abstract translation: 提供一种用于安装在其上的芯片的电子载板，其包括主体和多个焊盘。 焊盘具有用于通过导电凸块承载芯片的承载表面。 至少两个焊盘的承载表面相对于彼此相对地倾斜，从而防止安装在承载表面上的导电凸块的位移，从而进一步防止两个相邻的导电凸块经受位移而进入短路接触。

公开(公告)号：US07901995B2

公开(公告)日：2011-03-08

申请号：US11689558

申请日：2007-03-22

Applicant: Gabe Cherian

Inventor： Gabe Cherian

IPC: H01L21/60

CPC classification number: H05K3/3426 ,  H01L21/4853 ,  H01L21/6835 ,  H01L23/49555 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/72 ,  H01L24/73 ,  H01L24/742 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/0603 ,  H01L2224/1012 ,  H01L2224/11334 ,  H01L2224/1134 ,  H01L2224/11822 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/13124 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13582 ,  H01L2224/136 ,  H01L2224/13655 ,  H01L2224/1403 ,  H01L2224/16 ,  H01L2224/1601 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/4556 ,  H01L2224/45599 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73203 ,  H01L2224/73251 ,  H01L2224/73257 ,  H01L2224/81903 ,  H01L2224/85 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01043 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15331 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/3511 ,  H05K3/308 ,  H05K2201/09418 ,  H05K2201/10318 ,  H05K2201/10424 ,  H05K2201/10689 ,  H05K2201/10704 ,  H05K2201/10719 ,  H05K2201/10734 ,  H05K2201/10825 ,  H05K2201/10871 ,  H05K2201/10946 ,  H05K2201/10977 ,  H05K2203/0769 ,  Y02P70/613 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/29099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/72

Abstract: The present invention relates generally to permanent interconnections between electronic devices, such as integrated circuit packages, chips, wafers and printed circuit boards or substrates, or similar electronic devices. More particularly it relates to high-density electronic devices.The invention describes means and methods that can be used to counteract the undesirable effects of thermal cycling, shock and vibrations and severe environment conditions in general.For leaded devices, the leads are oriented to face the thermal center of the devices and the system they interact with.For leadless devices, the mounting elements are treated or prepared to control the migration of solder along the length of the elements, to ensure that those elements retain their desired flexibility.

Abstract translation: 本发明一般涉及电子设备之间的永久互连，例如集成电路封装，芯片，晶片和印刷电路板或基板或类似的电子设备。 更具体地说，涉及高密度电子设备。 本发明描述了可用于抵消热循环，冲击和振动以及恶劣环境条件的不良影响的手段和方法。 对于有铅器件，引线面向设备的热中心及其与之相互作用的系统。 对于无引线器件，安装元件被处理或准备好以控制沿着元件长度的焊料的迁移，以确保这些元件保持其期望的柔性。

公开(公告)号：US07863525B2

公开(公告)日：2011-01-04

申请号：US12404213

申请日：2009-03-13

Applicant: Shigenori Miyagawa

Inventor： Shigenori Miyagawa

IPC: H05K1/16 ,  H05K1/11 ,  H01R12/04

CPC classification number: H05K1/114 ,  H01L2224/48091 ,  H01L2224/48227 ,  H05K1/0271 ,  H05K3/429 ,  H05K2201/09418 ,  H05K2201/10734 ,  H01L2924/00014

Abstract: According to one embodiment, there is provided a printed circuit board including a plurality of electrode pads provided on a component mounting face on which a semiconductor component is to be mounted, a plurality of hole terminals provided on the component mounting face so as to correspond to the electrode pads, and a plurality of wiring pattern layers connecting the plurality of electrode pads and the plurality of hole terminals corresponding to the plurality of electrode pads, the plurality of wiring pattern layers being wired across directions of elastic deformation of the component mounting face.

Abstract translation: 根据一个实施例，提供了一种印刷电路板，其包括设置在其上将要安装半导体部件的部件安装面上的多个电极焊盘，设置在部件安装面上的多个孔端子，以对应于 所述电极焊盘和连接所述多个电极焊盘和与所述多个电极焊盘对应的所述多个孔端子的多个布线图案层，所述多个布线图案层在所述部件安装面的弹性变形方向上布线。