公开(公告)号：US09570313B2

公开(公告)日：2017-02-14

申请号：US14869330

申请日：2015-09-29

Applicant: Tokyo Electron Limited

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/311 ,  H01J37/32 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract translation: 描述了在基板上构图栅叠层的方法。 该方法包括在衬底上准备栅极堆叠，其中栅极堆叠包括形成在高k层上的高k层和栅极层。 该方法还包括使用脉冲偏置等离子体蚀刻工艺将形成在栅极层中的图案转移到高k层，以及选择用于脉冲偏压等离子体蚀刻工艺的工艺条件，以实现在衬底中形成的具有深度 小于2纳米（nm）。

公开(公告)号：US09165765B1

公开(公告)日：2015-10-20

申请号：US14481136

申请日：2014-09-09

Applicant: Tokyo Electron Limited

Inventor： Angelique D. Raley ,  Akiteru Ko

IPC: H01L21/4763 ,  H01L21/02 ,  H01L21/223

CPC classification number: H01L21/0234 ,  H01L21/02326 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/2236 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/32105

Abstract: Techniques include a plasma oxidation treatment to modify a material to a predetermined thickness around a mandrel or spacer or other structure. This plasma oxidation is then followed by a chemical oxide removal treatment. With only a portion of the structures being oxidized, or by selective masking a portion of oxidized structures, the chemical oxide removal treatment essentially shrinks only a portion of the structures, thereby yielding structures having differing critical dimensions which can function as etch masks to transfer patterns into one or more underlying layers. Accordingly, structures having differing critical dimensions can be fabricated at sub-resolution scales.

Abstract translation: 技术包括等离子体氧化处理以将材料修改成围绕心轴或间隔物或其它结构的预定厚度。 然后进行等离子体氧化，然后进行化学氧化物去除处理。 只有一部分结构被氧化，或者通过选择性掩蔽氧化结构的一部分，化学氧化物去除处理基本上只收缩一部分结构，从而产生具有不同临界尺寸的结构，其可用作蚀刻掩模以转移图案 进入一个或多个下层。 因此，具有不同临界尺寸的结构可以以亚分辨率尺度制造。

公开(公告)号：US09153457B2

公开(公告)日：2015-10-06

申请号：US14018329

申请日：2013-09-04

Applicant: Tokyo Electron Limited

Inventor： Vidhya Chakrapani ,  Akiteru Ko ,  Kaushik A. Kumar

IPC: H01L21/30 ,  H01L21/311 ,  H01L21/033 ,  H01L21/67

CPC classification number: H01L21/31138 ,  B81C1/00031 ,  B81C2201/0149 ,  G03F7/0002 ,  H01L21/0337 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67248

Abstract: A method for preparing a patterned directed self-assembly layer for reducing directed self-assembly pattern defectivity using direct current superpositioning is provided. A substrate having a block copolymer layer overlying a first intermediate layer, said block copolymer layer comprising a first phase-separated polymer defining a first pattern and a second phase-separated polymer defining a second pattern in said block copolymer layer is provided. A first plasma etching process using plasma formed of a first process composition to remove said second phase-separated polymer while leaving behind said first pattern of said first phase-separated polymer is performed. A second plasma etching process to transfer said first pattern into said first intermediate layer using plasma formed of a second process composition is performed. In an embodiment, said first phase-separated polymer is exposed to an electron beam preceding, during, or following said first plasma etching process, or preceding or during said second plasma etching process.

Abstract translation: 提供了一种用于使用直流叠加来制造用于减少定向自组装图案缺陷的图案化定向自组装层的方法。 提供了具有覆盖在第一中间层上的嵌段共聚物层的基材，所述嵌段共聚物层包含限定第一图案的第一相分离聚合物和在所述嵌段共聚物层中限定第二图案的第二相分离聚合物。 执行使用由第一处理组合物形成的等离子体的第一等离子体蚀刻工艺，以除去所述第二相分离聚合物，同时留下所述第一相分离聚合物的所述第一图案。 执行使用由第二处理组合物形成的等离子体将所述第一图案转印到所述第一中间层中的第二等离子体蚀刻工艺。 在一个实施方案中，所述第一相分离聚合物在所述第一等离子体蚀刻工艺之前，期间或之后或在所述第二等离子体蚀刻工艺之前或期间暴露于电子束。

公开(公告)号：US08945408B2

公开(公告)日：2015-02-03

申请号：US13918794

申请日：2013-06-14

Applicant: Tokyo Electron Limited

Inventor： Vidhya Chakrapani ,  Akiteru Ko ,  Kaushik Kumar

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  H01L21/311

CPC classification number: H01L21/31138 ,  B81C1/00031 ,  B81C2201/0149 ,  H01L21/0337 ,  H01L21/67103 ,  H01L21/67109 ,  H01L21/67248 ,  H01L22/12

Abstract: Provided is a method for preparing a patterned directed self-assembly layer, comprising: providing a substrate having a block copolymer layer comprising a first phase-separated polymer defining a first pattern in the block copolymer layer and a second phase-separated polymer defining a second pattern in the block copolymer layer; and performing an etching process to selectively remove the second phase-separated polymer while leaving behind the first pattern of the first phase-separated polymer on the surface of the substrate, the etching process being performed at a substrate temperature less than or equal to about 20 degrees C. The method further comprises providing a substrate holder for supporting the substrate, the substrate holder having a first temperature control element for controlling a first temperature at a central region and second temperature control element at an edge region of the substrate and setting a target value for the first and the second temperature.

Abstract translation: 提供了一种制备图案化定向自组装层的方法，包括：提供具有嵌段共聚物层的基材，所述嵌段共聚物层包含在嵌段共聚物层中限定第一图案的第一相分离聚合物和限定第二相分离聚合物的第二相分离聚合物 嵌段共聚物层中的图案; 并且执行蚀刻工艺以选择性地除去第二相分离聚合物，同时留下基材表面上的第一相分离聚合物的第一图案，蚀刻工艺在小于或等于约20的衬底温度下进行 该方法还包括提供用于支撑衬底的衬底保持器，衬底保持器具有用于控制中心区域的第一温度的第一温度控制元件和在衬底的边缘区域处的第二温度控制元件，并且设置靶 第一和第二温度的值。

公开(公告)号：US20140256149A1

公开(公告)日：2014-09-11

申请号：US14282716

申请日：2014-05-20

Applicant: TOKYO ELECTRON LIMITED

Inventor： Alok Ranjan ,  Akiteru Ko

IPC: H01L21/3065

CPC classification number: H01L21/3065 ,  H01J37/32082 ,  H01J37/3211 ,  H01J37/32137 ,  H01J37/32146 ,  H01J37/32165 ,  H01J37/3222 ,  H01J37/3244 ,  H01J37/32449 ,  H01J37/32697 ,  H01J37/32706 ,  H01J2237/334 ,  H01L21/28123 ,  H01L21/31116 ,  H01L21/31122 ,  H01L21/67069 ,  H01L21/6831 ,  H01L29/517 ,  H01L29/518

Abstract: A method of patterning a gate stack on a substrate is described. The method includes preparing a gate stack on a substrate, wherein the gate stack includes a high-k layer and a gate layer formed on the high-k layer. The method further includes transferring a pattern formed in the gate layer to the high-k layer using a pulsed bias plasma etching process, and selecting a process condition for the pulsed bias plasma etching process to achieve a silicon recess formed in the substrate having a depth less than 2 nanometer (nm).

Abstract translation: 描述了在基板上构图栅叠层的方法。 该方法包括在衬底上准备栅极堆叠，其中栅极堆叠包括形成在高k层上的高k层和栅极层。 该方法还包括使用脉冲偏置等离子体蚀刻工艺将形成在栅极层中的图案转移到高k层，以及选择用于脉冲偏压等离子体蚀刻工艺的工艺条件，以实现在衬底中形成的具有深度 小于2纳米（nm）。

公开(公告)号：US20250118532A1

公开(公告)日：2025-04-10

申请号：US18434253

申请日：2024-02-06

Applicant: Tokyo Electron Limited

Inventor： Sergey Voronin ,  Nicholas Smieszek ,  Qi Wang ,  Akiteru Ko ,  Carl Smith

IPC: H01J37/32 ,  H01L21/3065

Abstract: A method for plasma processing includes biasing a substrate by ramping a sheath voltage during a first phase of a plasma process and removing sidewall charge buildup on a feature of the substrate in an absence of substrate biasing during a second phase of the plasma process.

公开(公告)号：US11537049B2

公开(公告)日：2022-12-27

申请号：US16680989

申请日：2019-11-12

Applicant: Tokyo Electron Limited

Inventor： Toshiharu Wada ,  Chia-Yun Hsieh ,  Akiteru Ko

IPC: G03F7/16 ,  G03F7/20 ,  G03F7/004 ,  G03F1/22 ,  G03F7/00

Abstract: A substrate is provided with a patterned layer, for example, a photo resist layer, which may exhibit line roughness. In one exemplary embodiment, the patterned layer may be an extreme ultraviolet (EUV) photo resist layer. In one method, selective deposition of additional material is provided on the EUV photo resist layer after patterning to provide improved roughness and lithographic structure height to allow for more process margin when transferring the pattern to a layer underlying the photo resist. The additional material is deposited selectively thicker in areas above the photo resist than in areas where the photo resist is not present, such as exposed areas between the photo resist pattern. Pattern transfer to a layer underlying the photo resist may then occur (for example via an etch) while the patterned photo resist and additional material above the photo resist may collectively operate as an etch mask.

公开(公告)号：US11417526B2

公开(公告)日：2022-08-16

申请号：US16780248

申请日：2020-02-03

Applicant: Tokyo Electron Limited

Inventor： David L. O'Meara ,  Eric Chih-Fang Liu ,  Jodi Grzeskowiak ,  Anton deVilliers ,  Akiteru Ko ,  Anthony Dip

IPC: H01L21/033

Abstract: A method of forming a device includes depositing a first etch mask layer over a mandrel formed using a lithography process. The method includes depositing a second etch mask layer over the first etch mask layer. The method includes, using a first anisotropic etching process, etching the first etch mask layer and the second etch mask layer to form an etch mask including the first etch mask layer and the second etch mask layer. The method includes removing the mandrel to expose an underlying surface of the layer to be patterned. The method includes, using the etch mask, forming a feature by performing a second anisotropic etching process to pattern the layer to be patterned, where during the first anisotropic etching process, the first etch mask layer etches at a first rate and the second etch mask layer etches at a second rate, and where the first rate is different from the second rate.

公开(公告)号：US11380579B2

公开(公告)日：2022-07-05

申请号：US16864472

申请日：2020-05-01

Applicant: Tokyo Electron Limited

Inventor： Hirokazu Aizawa ,  Kaoru Maekawa ,  Akiteru Ko

IPC: H01L21/768 ,  H01L23/532

Abstract: A self-aligned multiple patterning (SAMP) multi-color spacer patterning process is disclosed for formation of structures on substrates. Trenches and vias may be formed in the process. A trench memorization layer and a via memorization layer may be formed on the substrate. In one embodiment, the trench memorization layer and the via memorization layer are formed between the multi-color spacer patterning structures and a low-k interlayer dielectric layer. The use of the trench memorization layer and the via memorization layer allows the formation of trenches and vias in the low-k interlayer dielectric layer without causing damage to the low-k properties of the low-k interlayer dielectric layer.

公开(公告)号：US20210265164A1

公开(公告)日：2021-08-26

申请号：US16851414

申请日：2020-04-17

Applicant: Tokyo Electron Limited

Inventor： Eric Chih-Fang Liu ,  Akiteru Ko ,  Angelique Raley ,  Henan Zhang ,  Shan Hu ,  Subhadeep Kal

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/3213 ,  H01L21/67 ,  H01L21/306

Abstract: In certain embodiments, a method of forming a semiconductor device includes forming a patterned resist layer over a hard mask layer using an extreme ultraviolet (EUV) lithography process. The hard mask layer is disposed over a substrate. The method includes patterning the hard mask layer using the patterned resist layer as an etch mask. The method includes smoothing the hard mask layer by forming, using a first atomic layer etch step, a first layer by converting a first portion of the hard mask layer, and by removing, using a second atomic layer etch step, the first layer.