公开(公告)号：US06489574B1

公开(公告)日：2002-12-03

申请号：US09702763

申请日：2000-11-01

Applicant: Toru Otaki ,  Hideho Inagawa ,  Toru Osaka

Inventor： Toru Otaki ,  Hideho Inagawa ,  Toru Osaka

IPC: H05K111

CPC classification number: H05K1/112 ,  H05K2201/09227 ,  H05K2201/09336 ,  H05K2201/0939 ,  H05K2201/09627 ,  H05K2201/10734

Abstract: A printed wiring board having assembled thereon a grid array type package, a multi-terminal device with many terminals arranged in matrix, is provided, through first signal connection holes, signal lines, and second connection holes, with many numbers of lands divided into plural blocks, being arranged in matrix on a first layer to connect each terminal of the multi-terminal device correspondingly, signal line patterns connected with many lands, and drawn out in the same direction per block, and first signal patterns from lands positioned on the innermost line of many lands. Then, the wiring patterns of the signal lines are drawn out regularly from many lands formed in matrix on the assembling surface of the grid array type package to make it easier for the printed wiring board to effectuate wiring connections without making them complicated or increasing the number of layers of the printed wiring board. Also, with the provision of ground patterns that surround signal lines, it is made possible to reduce unwanted radiant, as well as to suppress the occurrence of malfunctions of electronic equipment due to reflections and ground bounces.

Abstract translation: 在其上组装有格栅阵列型封装的印刷电路板，具有以矩阵形式布置的许多端子的多端子装置，通过第一信号连接孔，信号线和第二连接孔提供，其中多个焊盘被分成多个 块，以矩阵形式布置在第一层上，以相应地连接多终端设备的每个终端，与许多焊盘相连并沿与每块相同的方向拉出的信号线图案，以及位于最内层的焊盘的第一信号图案 许多土地线。 然后，信号线的布线图案从栅格阵列型封装的组装面上的矩阵状的多个区域中规则地拉出，使得印刷布线板更容易实现布线连接而不使其复杂或增加数量 的印刷线路板的层。 而且，通过提供围绕信号线的接地图案，可以减少不必要的辐射，并且抑制由于反射和地面反弹引起的电子设备故障的发生。

公开(公告)号：US6115262A

公开(公告)日：2000-09-05

申请号：US93025

申请日：1998-06-08

Applicant: Bjoern Erik Brunner ,  Vivek Amir Jairazbhoy ,  Richard Keith McMillan

Inventor： Bjoern Erik Brunner ,  Vivek Amir Jairazbhoy ,  Richard Keith McMillan

IPC: H05K1/11 ,  H05K3/34 ,  H05K1/18 ,  H05K7/06

CPC classification number: H05K3/3442 ,  H05K1/111 ,  H05K2201/09381 ,  H05K2201/0939 ,  H05K2201/10636 ,  H05K2203/0465 ,  H05K3/3484 ,  Y02P70/611 ,  Y02P70/613

Abstract: There is disclosed herein a printed circuit board (PCB) having enhanced mounting pads useful for overprinting solder paste and for repair of the solder joints. The PCB comprises: a dielectric substrate 10 having at least one mounting pad 20 thereon, wherein each mounting pad is arranged in matched relation with a respective termination 32 of an electronic component 30. Each mounting pad 20 includes a main body portion 24 and one or more fingerlike extensions 26 extending outward from the main body portion and away from a projected footprint 34 of the electronic component.

公开(公告)号：US20240215159A1

公开(公告)日：2024-06-27

申请号：US18131019

申请日：2023-04-05

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Sang-min Lee ,  Youngil Cho

IPC: H05K1/03 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/0353 ,  H05K1/111 ,  H05K1/115 ,  H05K3/0017 ,  H05K3/103 ,  H05K2201/0939 ,  H05K2201/099

Abstract: A circuit board according to an embodiment includes: a first insulating layer that does not include a reinforcing material; a conductive pad that protrudes above a surface of the first insulating layer, and a second insulating layer that is disposed below the first insulating layer and includes a reinforcing material. A corner of the conductive pad has a curved shape.

公开(公告)号：US12017080B2

公开(公告)日：2024-06-25

申请号：US17879575

申请日：2022-08-02

Applicant: Curonix LLC

Inventor： Laura Tyler Perryman ,  Graham Patrick Greene ,  Benjamin Speck ,  Patrick Larson ,  Paul Lombard

IPC: A61N1/375 ,  A61N1/05 ,  A61N1/372 ,  A61N1/378 ,  H01Q1/27 ,  H01Q1/38 ,  H05K1/11 ,  H05K1/18

CPC classification number: A61N1/375 ,  A61N1/05 ,  A61N1/37205 ,  A61N1/3787 ,  A61N1/37229 ,  H01Q1/273 ,  H01Q1/38 ,  H05K1/118 ,  H05K1/189 ,  H05K2201/0939

Abstract: An implantable electronic device includes a flexible circuit board, one or more circuit components attached to the flexible circuit board and configured to convert electrical energy into electrical pulses, and one or more electrodes attached to the flexible circuit board without cables connecting the electrodes to each other or to the flexible circuit board, the one or more electrodes configured to apply the electrical pulses to a tissue adjacent the implantable electronic device.

公开(公告)号：US20240196517A1

公开(公告)日：2024-06-13

申请号：US18585714

申请日：2024-02-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngsun JO ,  Dohoon KIM ,  Sangyong KIM ,  Bongkyu MIN ,  Seoyoung PARK ,  Yunoh CHI

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/14

CPC classification number: H05K1/0219 ,  H05K1/116 ,  H05K1/14 ,  H05K2201/0939 ,  H05K2201/10378

Abstract: Disclosed is an electronic device. The electronic device includes: a housing, a first board and a second board disposed in an interior of the housing, and an interposer electrically connecting the first board and the second board, the interposer includes a first part that defines an outer surface thereof, and a second part that defines an inner surface thereof, vias included in the first part are all ground vias and are spaced apart from each other by a first interval, and the vias included in the second part include signal vias, and ground vias, the number of which is less than that of the signal vias, and may be spaced apart from each other by a second interval that is larger than or equal to the first interval.

公开(公告)号：US20240098896A1

公开(公告)日：2024-03-21

申请号：US18463728

申请日：2023-09-08

Applicant: PanelSemi Corporation

Inventor： Chin-Tang LI ,  Chao-Jung CHEN

IPC: H05K1/11 ,  H05K1/18

CPC classification number: H05K1/113 ,  H05K1/181 ,  H05K2201/09227 ,  H05K2201/0939 ,  H05K2201/09481 ,  H05K2201/096 ,  H05K2201/09854

Abstract: An electronic device includes a first substrate, a second substrate, plural conductive pads, plural hole structures, plural connection pads and plural conductive structures. Hole structures penetrate through the first and second substrates, and are arranged corresponding to the conductive pads. Second ends of hole structures are located at the second substrate, and the corresponding conductive pad is exposed by one of the second ends. Connection pads enclose first ends of hole structures. Conductive structures are arranged in the hole structures and electrically connected to corresponding conductive pads and connection pads. The second diameter portion of each conductive structure penetrates through first substrate and conductive pad and is electrically connected to corresponding connection pad and conductive pad, and first diameter portion thereof penetrates through second substrate and is electrically connected to corresponding conductive pad. Each conductive pad defines an opening, which is exposed by second end of corresponding hole structure.

公开(公告)号：US20240098895A1

公开(公告)日：2024-03-21

申请号：US18355167

申请日：2023-07-19

Applicant: Jabil Inc.

Inventor： Lun Hao Tung ,  Lai Ming Lim ,  Zambri Samsudin

IPC: H05K1/11 ,  H05K1/02 ,  H05K1/18

CPC classification number: H05K1/111 ,  H05K1/0283 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/0939

Abstract: A bond pad connector to be disposed on a stretchable substrate and adapted to secure an electronic component thereon. The bond pad connector includes two spaced apart bond pads that are adapted to be disposed on the stretchable substrate to face each other. Each of the two bond pads is adapted to be connected to a respective conductive trace and includes: a stress relieve component that is adapted to be connected to the conductive trace, the stress relieve component being formed with a central hole; and an extension component extending from the stress relieve component and opposite to the conductive trace. The electronic component is secured onto the bond pad connector by attaching the electronic component to, for each of the bond pads, at least a part of the extension component.

公开(公告)号：US20180213644A1

公开(公告)日：2018-07-26

申请号：US15880670

申请日：2018-01-26

Applicant: IBIDEN CO., LTD.

Inventor： Hiroyasu Noto ,  Yoshinori Takenaka

IPC: H05K1/11 ,  H05K1/03

CPC classification number: H05K1/113 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H05K1/0373 ,  H05K1/116 ,  H05K2201/0209 ,  H05K2201/0257 ,  H05K2201/0266 ,  H05K2201/068 ,  H05K2201/0939 ,  H05K2201/09509 ,  H05K2201/09827

Abstract: A printed wiring board includes an interlayer resin insulating layer including resin and inorganic particles, a via conductor formed through the insulating layer, a first conductor layer formed on the first surface of the insulating layer and including a land portion of the via conductor on the first surface, and a second conductor layer formed on second surface of the insulating layer and connected to bottom of the via conductor. The bottom of the via conductor has diameter of 20 to 35 μm, the first conductor layer has thickness of 3 to 12 μm, the insulating layer has thickness of 1 to 15 μm, the second conductor layer has thickness of 1 to 12 μm, and the second conductor and insulating layers are formed such that T1/T2 is 0.06 to 7.00 where T1 represents the thickness of the second conductor layer, and T2 represents the thickness of the insulating layer.

公开(公告)号：US09995894B2

公开(公告)日：2018-06-12

申请号：US15028934

申请日：2014-10-08

Applicant: ams AG

Inventor： Jochen Kraft ,  Karl Rohracher ,  Jordi Teva

IPC: G02B6/12 ,  H01L21/00 ,  H01L23/48 ,  H01L31/16 ,  G02B6/42 ,  G02B6/43 ,  H05K1/02 ,  H05K1/11 ,  G02B6/13 ,  H05K1/18 ,  H05K3/42 ,  H05K3/46

CPC classification number: G02B6/4283 ,  G02B6/12002 ,  G02B6/13 ,  G02B6/4274 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/121 ,  G02B2006/12107 ,  G02B2006/12121 ,  G02B2006/12123 ,  G02B2006/12147 ,  H01L23/481 ,  H01L23/522 ,  H01L31/16 ,  H01L2224/16225 ,  H05K1/0274 ,  H05K1/115 ,  H05K1/116 ,  H05K1/181 ,  H05K3/429 ,  H05K3/4605 ,  H05K2201/0939 ,  H05K2201/09518 ,  H05K2201/09581 ,  H05K2201/10174

Abstract: The method comprises providing a semiconductor substrate, which has a main surface and an opposite further main surface, arranging a contact pad above the further main surface, forming a through-substrate via from the main surface to the further main surface at a distance from the contact pad and, by the same method step together with the through-substrate via, forming a further through-substrate via above the contact pad, arranging a hollow metal via layer in the through-substrate via and, by the same method step together with the metal via layer, arranging a further metal via layer in the further through-substrate via, the further metal via layer contacting the contact pad, and removing a bottom portion of the metal via layer to form an optical via laterally surrounded by the metal via layer.

公开(公告)号：US20180063953A1

公开(公告)日：2018-03-01

申请号：US15677395

申请日：2017-08-15

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Jung Yun JO ,  Jeong Do YANG

IPC: H05K1/11 ,  H05K3/18 ,  H05K3/28 ,  H05K3/40

CPC classification number: H05K1/111 ,  H05K1/0313 ,  H05K1/09 ,  H05K3/188 ,  H05K3/28 ,  H05K3/36 ,  H05K3/4007 ,  H05K2201/0314 ,  H05K2201/0367 ,  H05K2201/09045 ,  H05K2201/0939 ,  H05K2201/10128 ,  H05K2201/10136 ,  H05K2203/0723

Abstract: A circuit board, a display device including the same, and a method of manufacturing a circuit board are provided. A circuit board includes a base substrate, a wiring line provided on the base substrate, a passivation layer provided on the wiring line, an elastic bump provided on the passivation layer, and a conductive layer provided on the elastic bump. The passivation layer includes a first opening and a second opening that expose a partial region of the wiring line, and the second opening is arranged in a region adjacent to the first opening.