公开(公告)号：US20100108369A1

公开(公告)日：2010-05-06

申请号：US12262979

申请日：2008-10-31

Applicant: Alexander Tom

Inventor： Alexander Tom

IPC: H05K1/11 ,  H05K1/16 ,  H01R43/00 ,  G06F17/50

CPC classification number: H05K1/162 ,  H03H7/0115 ,  H05K1/0251 ,  H05K1/116 ,  H05K3/429 ,  H05K2201/09454 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/097 ,  H05K2201/09718 ,  H05K2201/09727 ,  Y10T29/4921

Abstract: Printed circuit board capacitors include a first electrode comprising a via extending at least partially through a multi-layer printed circuit board and a plurality of conductive pads in electrical contact with the via and extending radially outward from the via, and a second electrode electrically isolated from the first electrode and comprising a plurality of ground-plane layers of the printed circuit board. The plurality of ground-plane layers include electrically conductive material overlapping the plurality of conductive pads.

Abstract translation: 印刷电路板电容器包括第一电极，其包括至少部分延伸穿过多层印刷电路板的通孔和与通孔电接触并从通孔径向向外延伸的多个导电焊盘，以及与通孔电绝缘的第二电极 所述第一电极并且包括所述印刷电路板的多个接地层。 多个接地层包括与多个导电焊盘重叠的导电材料。

公开(公告)号：US20100096725A1

公开(公告)日：2010-04-22

申请号：US12523587

申请日：2008-02-04

Applicant: Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

Inventor： Hao Shi ,  Jung-Hoon Chun ,  Xingchao Yuan

IPC: H01L23/488 ,  H01L21/60 ,  G06F17/50

CPC classification number: H01L23/49838 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/645 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05552 ,  H01L2224/05553 ,  H01L2224/05555 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/3011 ,  H05K1/112 ,  H05K1/165 ,  H05K3/4602 ,  H05K2201/09627 ,  H05K2201/10674 ,  H01L2924/00

Abstract: In some embodiments, the semiconductor package includes a substrate having multiple layers, from a first layer to a final layer, a die coupled to the first layer, an electrical connector such as a solder ball coupled to the final layer, and a spiral trace disposed and electrically coupled between the die and the electrical connector. Inductance of the spiral trace is selected such that the package has a predetermined impedance. Material, cross-sectional area, number and density of windings, and total overall length of the spiral trace are selected accordingly. In other embodiments, the semiconductor package includes a substrate with multiple layers; a die coupled to the first of the layers; an electrical connector coupled to the final layer; and a spiral trace, in or on the substrate. The spiral trace is near the die, and electrically coupled between the die and the electrical connector.

Abstract translation: 在一些实施例中，半导体封装包括具有多个层的衬底，从第一层到最终层，耦合到第一层的管芯，耦合到最终层的焊球等电连接器以及布置在其上的螺旋迹线 并且电连接在管芯和电连接器之间。 选择螺旋迹线的电感，使得封装具有预定的阻抗。 相应地选择材料，横截面积，绕组的数量和密度以及螺旋迹线的总长度。 在其他实施例中，半导体封装包括具有多层的衬底; 耦合到第一层的管芯; 耦合到最终层的电连接器; 以及衬底中或衬底上的螺旋迹线。 螺旋迹线靠近模具，并且电连接在管芯和电连接器之间。

公开(公告)号：US07671450B2

公开(公告)日：2010-03-02

申请号：US12060387

申请日：2008-04-01

Applicant: Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

Inventor： Ellis E. Nease ,  Ashley Rebelo ,  Christopher J. Wittensoldner

IPC: H01L23/50

CPC classification number: H05K1/0251 ,  H01L23/49827 ,  H01L23/66 ,  H01L2223/6616 ,  H01L2223/6638 ,  H01L2924/0002 ,  H01L2924/19051 ,  H01L2924/3011 ,  H05K1/0245 ,  H05K1/115 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/09727 ,  H01L2924/00

Abstract: An integrated circuit package having a multi-segment transmission line transformer for impedance matching a packaged integrated circuit, such as a driver or receiver, to a printed circuit board (PCB) transmission line to which the packaged chip is attached by, for example, solder balls. In one exemplary embodiment, a three-segment transmission line transformer provides improved broadband performance with the advantage of having a middle segment with a flexible length for easier routing. The length of each end segment of the three-segment transformer is adjusted to provide at least partial cancellation of reflections between the PCB and the transformer, and between the transformer and a circuit on the integrated circuit, respectively. Further, the inductive reactance of the solder balls and via wiring may be cancelled out by the transformed chip impedance to provide a non-inductive termination to the PCB transmission line at approximately one-half the highest data rate of the channel.

Abstract translation: 一种具有多段传输线变压器的集成电路封装，用于将封装集成电路（例如驱动器或接收器）与包装芯片通过例如焊料连接到的印刷电路板（PCB）传输线进行阻抗匹配 球。 在一个示例性实施例中，三段式传输线变压器提供了改进的宽带性能，其优点在于具有具有灵活长度的中间段以便于路由。 三段式变压器的每个端段的长度被调整以分别提供PCB和变压器之间以及变压器与集成电路上的电路之间的反射的至少部分消除。 此外，焊球和通孔布线的感抗可能被转换的芯片阻抗抵消，以便以通道的最高数据速率的大约一半提供对PCB传输线的非感性端接。

公开(公告)号：US20100012367A1

公开(公告)日：2010-01-21

申请号：US11722342

申请日：2005-12-14

Applicant: Marc Andre De Samber ,  Koen Van Os

Inventor： Marc Andre De Samber ,  Koen Van Os

IPC: H05K1/11

CPC classification number: H05K1/0206 ,  H05K1/0263 ,  H05K2201/09509 ,  H05K2201/09609 ,  H05K2201/09627 ,  H05K2201/09672 ,  H05K2201/09781

Abstract: The present invention relates to a printed circuit board arrangement with a multi-layer substrate (1, 2) having a buried conductor (4) and a contact area (3), connected to the conductor (4) and being disposed on a surface of the substrate. In order to improve the cooling of the buried conductor, a metal cooling area (6) is provided above the conductor (4), and is connected to the conductor by means of one or more via conductors (7).

Abstract translation: 本发明涉及具有多层衬底（1,2）的印刷电路板装置，该多层衬底具有埋入导体（4）和与该导体（4）连接的接触区域（3） 底物。 为了改善掩埋导体的冷却，金属冷却区域（6）设置在导体（4）上方，并通过一个或多个通孔导体（7）与导体连接。

公开(公告)号：US20090289734A1

公开(公告)日：2009-11-26

申请号：US12353312

申请日：2009-01-14

Applicant: Tzong-Lin Wu ,  Ting-Kuang Wang ,  Hao-Hsieh Chuang ,  Chia-Yuan Hsieh

Inventor： Tzong-Lin Wu ,  Ting-Kuang Wang ,  Hao-Hsieh Chuang ,  Chia-Yuan Hsieh

IPC: H04B3/28

CPC classification number: H05K1/0236 ,  H01L23/552 ,  H01L2924/0002 ,  H05K2201/09309 ,  H05K2201/09627 ,  H05K2201/09781 ,  H01L2924/00

Abstract: Proposed is an apparatus for silencing electromagnetic noise, characterized by a plurality of centrally symmetrical ring-shaped through-via-hole crystalline units provided between a high voltage plane and a low voltage plane at a regular interval, thereby forming an omnidirectional noise suppression frequency band for reducing noise interference and electromagnetic radiation. In a first embodiment of the ring-shaped through-via-hole crystalline units, the through via holes are perpendicularly coupled between a metal plane and the low voltage plane. In a second embodiment of the ring-shaped through-via-hole crystalline units, the through via holes are perpendicularly coupled between two metal planes. Positioned at a regular interval, the through via holes enable provision of omnidirectional noise suppression frequency band, simplified design of a power plane, and reduction of production costs.

Abstract translation: 提出了一种用于消除电磁噪声的装置，其特征在于以规则的间隔设置在高压面和低压面之间的多个中心对称的环形通孔结晶单元，从而形成全向噪声抑制频带 用于减少噪音干扰和电磁辐射。 在环形通孔结晶单元的第一实施例中，通孔垂直地耦合在金属平面和低压平面之间。 在环形通孔结晶单元的第二实施例中，贯通通孔垂直耦合在两个金属平面之间。 通过定时间隔定位，通孔可提供全向噪声抑制频带，简化电力平面设计，降低生产成本。

公开(公告)号：US07612634B2

公开(公告)日：2009-11-03

申请号：US11723359

申请日：2007-03-19

Applicant: Masashi Iwata

Inventor： Masashi Iwata

IPC: H03H9/70

CPC classification number: H05K1/0243 ,  H03H7/463 ,  H03H9/725 ,  H03H2001/0085 ,  H04B1/0057 ,  H05K1/0298 ,  H05K1/112 ,  H05K1/181 ,  H05K2201/09627 ,  H05K2201/09636 ,  H05K2201/1003 ,  H05K2201/10083

Abstract: A high frequency module incorporates a layered substrate. The layered substrate has a bottom surface and a top surface. Terminals are disposed on the bottom surface. SAW filters and inductors are mounted on the top surface. The layered substrate incorporates: a first conductor layer connecting the SAW filters to the inductors; a second conductor layer connected to the terminals and disposed at a location closer to the bottom surface than the first conductor layer; and a plurality of parallel signal paths each of which is formed using at least one through hole provided inside the layered substrate and each of which connects the first and second conductor layers to each other.

Abstract translation: 高频模块结合了层状衬底。 层状基板具有底面和顶面。 端子设置在底面。 SAW滤波器和电感器安装在顶面上。 层状衬底包括：将SAW滤波器连接到电感器的第一导体层; 连接到端子并且设置在比第一导体层更靠近底表面的位置处的第二导体层; 以及多个并行信号路径，每个平行信号路径使用设置在分层基板内部的至少一个通孔形成，并且每个通孔将第一和第二导体层彼此连接。

公开(公告)号：US07595546B2

公开(公告)日：2009-09-29

申请号：US11548431

申请日：2006-10-11

Applicant: Shoji Matsumoto

Inventor： Shoji Matsumoto

IPC: H01L23/64 ,  H05K7/00 ,  H04B3/28

CPC classification number: H05K1/0216 ,  H01L2924/0002 ,  H05K1/0245 ,  H05K1/025 ,  H05K1/181 ,  H05K2201/09236 ,  H05K2201/09627 ,  H05K2201/10189 ,  H05K2201/10689 ,  H01L2924/00

Abstract: Impedance mismatching points such as a VIA and a connector on a differential line between a differential driver element and a differential receiver element are arranged in predetermined positions. That is, the impedance mismatching points are arranged in such positions that a transmission time of a digital signal transmitted through a main differential line becomes (integral multiple of UI)±0.5×Trf, whereby noises are generated within the rise and fall times of a signal to be able to maintain an excellent waveform of the signal.

Abstract translation: 诸如差分驱动器元件和差分接收器元件之间的差分线路上的VIA和连接器的阻抗不匹配点被布置在预定位置。 也就是说，阻抗失配点被布置在通过主差分线发送的数字信号的发送时间变为（UI的整数倍）±0.5×Trf的位置，从而在信号的上升和下降时间内产生噪声 能够保持良好的信号波形。

公开(公告)号：US20090231819A1

公开(公告)日：2009-09-17

申请号：US12331769

申请日：2008-12-10

Applicant: Yoshiaki SATAKE ,  Taihei Nakada

Inventor： Yoshiaki SATAKE ,  Taihei Nakada

IPC: H05K1/18

CPC classification number: H05K1/0253 ,  H05K1/0224 ,  H05K1/025 ,  H05K3/429 ,  H05K2201/0191 ,  H05K2201/0715 ,  H05K2201/09336 ,  H05K2201/09627 ,  H05K2201/09845 ,  H05K2201/09972

Abstract: A multilayer substrate has a 1st strip line, a 2nd strip line and the 3rd strip line, and those characteristic impedances are different each other. The third strip line has a strip conductor of which length is equivalent to ¼ wavelength of an operating frequency. A strip conductor of the third strip line is the same conductor as a strip conductor of the first strip line, and is a different conductor layer from a strip conductor of the second strip line. Ground conductors of the 3rd strip line are formed of the same conductor layer as one of a ground conductor of the 1st strip line, and the same conductor layer as one of a ground conductor of the 2nd strip line. The strip conductor of the second strip line and the strip conductor of the third strip line are connected through via hole arranged in the multilayer substrate.

Abstract translation: 多层基板具有第一带状线，第二带状线和第三带状线，并且那些特性阻抗彼此不同。 第三带状线具有条形导体，其长度等于工作频率的1/4波长。 第三带状线的带状导体是与第一带状线的带状导体相同的导体，并且是与第二带状线的带状导体不同的导体层。 第三带状线的接地导体由与第一带状线的接地导体中的一个相同的导体层和与第二带状线的接地导体之一相同的导体层形成。 第二带状带的带状导体和第三条带的带状导体通过设置在多层基板中的通孔连接。

公开(公告)号：US20090219045A1

公开(公告)日：2009-09-03

申请号：US12039854

申请日：2008-02-29

Applicant: Michael CARNEY ,  Marek Reksnis ,  Ted Toth

Inventor： Michael CARNEY ,  Marek Reksnis ,  Ted Toth

IPC: G01R31/02 ,  H05K3/32

CPC classification number: H05K1/116 ,  G01R1/07314 ,  G01R3/00 ,  H05K3/3447 ,  H05K3/429 ,  H05K2201/09627 ,  H05K2201/10303 ,  Y10T29/49124

Abstract: There is disclosed an electronic testbed, an electronic testbed board, and a method for positioning receptacles for nails in the electronic testbed board. In an embodiment, the electronic testbed board includes a mounting through-hole for mounting a receptacle for a nail. The mounting through-hole is drilled to a suitably precise diameter for mounting the receptacle substantially perpendicular to the testbed board. One or more via-holes are located adjacent the mounting through-hole, and are adapted to allow an electrical connection between any conductive layers provided at the one or more via-holes. The receptacle may be mounted more accurately and the electronic test bed may be built more accurately by separating the functions of the via-holes and the mounting through-hole.

Abstract translation: 公开了一种电子测试台，电子测试台和用于在电子测试台中定位钉子的插座的方法。 在一个实施例中，电子测试台板包括用于安装用于钉子的插座的安装通孔。 将安装通孔钻入适当精确的直径，以将基座垂直于测试台板安装。 一个或多个通孔位于安装通孔附近，并且适于允许在一个或多个通孔处提供的任何导电层之间的电连接。 可以更准确地安装插座，并且可以通过分离通孔和安装通孔的功能来更准确地构建电子测试台。

公开(公告)号：US07568922B2

公开(公告)日：2009-08-04

申请号：US11304770

申请日：2005-12-16

Applicant: Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

Inventor： Takahiro Yamashita ,  Hiroyuki Watanabe ,  Kiyotaka Tsukada ,  Michio Ido ,  Morio Nakao

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H01L23/49816 ,  H01L23/49827 ,  H01L24/48 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H05K1/113 ,  H05K3/3457 ,  H05K2201/0347 ,  H05K2201/09436 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09627 ,  H05K2201/098 ,  Y10T29/49144 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: This invention provides a printed wiring board having an intensified drop impact resistance of a joint portion between pad and solder. An electrode pad comprises pad portion loaded with solder ball and a cylindrical portion projecting to the solder ball supporting the pad portion. An outer edge of the pad portion extends sideway from a cylindrical portion so that the outer edge is capable of bending. If the outer edge bends when stress is applied to the solder ball 30, stress on the outer edge of the pad portion on which stress is concentrated can be relaxed so as to intensify the joint strength between an electrode pad and solder ball.

Abstract translation: 本发明提供了一种印刷电路板，其具有焊盘和焊料之间的接合部分的强烈的耐滴落冲击性。 电极焊盘包括装载有焊球的焊盘部分和突出到支撑焊盘部分的焊球的圆柱形部分。 衬垫部分的外边缘从圆筒部分侧向延伸，使得外边缘能够弯曲。 如果当对焊球30施加应力时外边缘弯曲，则可以放松应力集中的焊盘部分的外边缘上的应力，从而加强电极焊盘和焊球之间的接合强度。