公开(公告)号：US20130048360A1

公开(公告)日：2013-02-28

申请号：US13497881

申请日：2010-09-24

Applicant: Stijn Vandebril

Inventor： Stijn Vandebril

IPC: B23K1/20 ,  H05K1/11

CPC classification number: H05K3/3436 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/112 ,  H05K3/284 ,  H05K3/3494 ,  H05K2201/09063 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: Method for providing a printed circuit board (16) with an electronic device (1), wherein the electronic device (1) having at least one external soldering pad (11) having a predetermined size for heat dissipation is soldered with the soldering pad (11) onto a printed circuit board substrate of the printed circuit board (16) such that the electronic device (1) is electrically connected to an electrical circuit provided on the printed circuit board substrate, wherein prior to soldering, one or more through holes (12) are provided in the printed circuit board in the area where the soldering pad (12) is to be soldered to the printed circuit board (16) such that the through hole is provided for allowing flux gasses resulting during soldering of the electronic device (1) to the printed circuit board to escape.

Abstract translation: 一种用于向电子设备（1）提供印刷电路板（16）的方法，其中具有至少一个具有预定尺寸用于散热的外部焊盘（11）的电子设备（1）用焊盘（11）焊接 ）印刷到印刷电路板（16）的印刷电路板基板上，使得电子器件（1）电连接到设置在印刷电路板基板上的电路，其中在焊接之前，一个或多个通孔（12 ）设置在要焊接到印刷电路板（16）的焊盘（12）的区域中的印刷电路板中，使得通孔被设置成允许在焊接电子设备（1）期间产生的通量气体 ）到印刷电路板上逃逸。

公开(公告)号：US20130044435A1

公开(公告)日：2013-02-21

申请号：US13497890

申请日：2010-09-24

Applicant: Stijn Vandebril

Inventor： Stijn Vandebril

IPC: H05K7/06 ,  H05K7/20

CPC classification number: H05K3/3436 ,  H01L2224/16225 ,  H01L2924/19105 ,  H01L2924/19107 ,  H05K1/0203 ,  H05K1/111 ,  H05K1/112 ,  H05K3/284 ,  H05K3/3494 ,  H05K2201/09063 ,  H05K2201/09127 ,  H05K2201/09472 ,  H05K2201/0969 ,  H05K2203/1178 ,  Y02P70/611 ,  Y02P70/613

Abstract: System in package including a substrate having a first external layer including a first conductive patterned layer and being externally accessible for electrically connecting the system in package to an external electric circuit and a second internal layer including a second conductive patterned layer and being covered by the first layer and electronic devices provided on the substrate and electrically connected to external contact pads of the first conductive patterned layer. The devices and the first and second conductive patterned layer being electrically connected to form an internal electric circuit electronically connected to the external electric circuit, the first and the second layer being adjacently positioned, the electronic devices being enclosed in an overmould compound. At least one of the devices is electrically connected to at least one hidden contact pad of the second conductive patterned layer which is accessible after removal of a removable strip of the first layer.

Abstract translation: 包括系统的包括具有包括第一导电图案化层的第一外部层并且可外部访问的衬底的衬底，用于将封装中的系统电连接到外部电路，以及包括第二导电图案层的第二内部层并且被第一 层和电子器件，其设置在基板上并电连接到第一导电图案化层的外部接触焊盘。 所述器件和第一和第二导电图案层电连接以形成电连接到外部电路的内部电路，第一和第二层相邻定位，电子器件封装在覆盖模制化合物中。 至少一个器件电连接到第二导电图案化层的至少一个隐藏的接触焊盘，该隐形接触焊盘在移除第一层的可移除带之后是可接近的。

公开(公告)号：US08274634B2

公开(公告)日：2012-09-25

申请号：US12485624

申请日：2009-06-16

Applicant: Harutoshi Oikawa ,  Kiyohiro Kimura

Inventor： Harutoshi Oikawa ,  Kiyohiro Kimura

IPC: G02F1/1345

CPC classification number: H05K3/361 ,  G06F3/045 ,  H05K3/281 ,  H05K3/323 ,  H05K3/421 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09481 ,  H05K2201/09563 ,  H05K2201/097 ,  H05K2201/0979 ,  H05K2203/1572

Abstract: A flexible printed circuit includes: a first wiring layer and a second wiring layer being in contact with one surface of a flexible substrate, a third wiring layer and a fourth wiring layer on the other surface of the flexible substrate, a first conductive member being formed on surfaces in proximity to a through hole of the second wiring layer and the fourth wiring layer; a second conductive member being formed on surfaces in proximity to the first end section of the first wiring layer and the third wiring layer; and an insulating layer being formed in a space between the first wiring layer and the second conductive member, and the second wiring layer and the first conductive member and a space between the third wiring layer and the second conductive member, and the fourth wiring layer and the first conductive member.

Abstract translation: 柔性印刷电路包括：第一布线层和与柔性基板的一个表面接触的第二布线层，在柔性基板的另一个表面上的第三布线层和第四布线层，形成第一导电部件 在第二布线层和第四布线层的通孔附近的表面上; 第二导电构件形成在靠近第一布线层和第三布线层的第一端部的表面上; 以及在所述第一布线层和所述第二导电构件之间的空间中形成绝缘层，以及所述第二布线层和所述第一导电构件以及所述第三布线层和所述第二导电构件之间的空间，以及所述第四布线层和 第一导电构件。

公开(公告)号：US08254134B2

公开(公告)日：2012-08-28

申请号：US12684841

申请日：2010-01-08

Applicant: Siew S. Hiew ,  Abraham C. Ma ,  Nan Nan

Inventor： Siew S. Hiew ,  Abraham C. Ma ,  Nan Nan

IPC: H05K7/02

CPC classification number: H05K3/284 ,  H01L21/565 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/14 ,  H01L2924/19105 ,  H01L2924/3025 ,  H05K1/117 ,  H05K1/141 ,  H05K2201/09472 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10446 ,  H05K2203/1316 ,  Y10T29/4913 ,  H01L2924/00012 ,  H01L2224/85 ,  H01L2924/00

Abstract: A Secure Digital device including a PCBA having passive components mounted on a PCB using surface mount technology (SMT) techniques, and active components (e.g., controller and flash memory) mounted using chip-on-board (COB) techniques. The components are mounted only on one side of the PCB, and then a molded plastic casing is formed over both sides of the PCB such that the components are encased in the plastic, and a thin plastic layer is formed over the PCB surface opposite to the components. The molded plastic casing is formed to include openings that expose metal contacts provided on the PCB, and ribs that separate the openings. The molded plastic casing defines a pre-molded switch slot that facilitates an insert-in switch assembly process for mounting a write protect switch. The write protect switch includes a movable switch button engaged in the switch slot, and a switch cap secured over the switch slot.

Abstract translation: 一种安全数字设备，包括使用表面贴装技术（SMT）技术安装在PCB上的无源元件的PCBA以及使用板上（COB）技术安装的有源组件（例如，控制器和闪存）。 组件仅安装在PCB的一侧，然后在PCB的两侧形成模制塑料外壳，使得部件被包装在塑料中，并且在PCB表面上形成薄的塑料层 组件。 模制的塑料外壳形成为包括露出设置在PCB上的金属触点的开口和分开开口的肋。 模制的塑料外壳限定了预先模制的开关槽，其有助于插入开关组装过程以安装写保护开关。 写保护开关包括接合在开关槽中的可移动开关按钮和固定在开关槽上的开关帽。

公开(公告)号：US08248093B2

公开(公告)日：2012-08-21

申请号：US12837649

申请日：2010-07-16

Applicant: Sang-Guk Han ,  Seok-Joon Moon

Inventor： Sang-Guk Han ,  Seok-Joon Moon

IPC: G01R31/00

CPC classification number: H01L25/0657 ,  G01R31/2808 ,  G01R31/2818 ,  G11C5/02 ,  G11C5/025 ,  G11C5/06 ,  G11C29/04 ,  G11C29/12 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/5602 ,  H01L22/30 ,  H01L22/32 ,  H01L23/49811 ,  H01L23/49838 ,  H01L23/538 ,  H01L24/09 ,  H01L24/48 ,  H01L24/49 ,  H01L24/80 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/18 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/0912 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/4912 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/01068 ,  H01L2924/181 ,  H05K1/0268 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/002 ,  H05K3/245 ,  H05K3/28 ,  H05K3/288 ,  H05K3/323 ,  H05K2201/0187 ,  H05K2201/035 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/099 ,  H05K2201/10159 ,  H05K2203/162 ,  Y10T29/49117 ,  Y10T29/49155 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: An electronic device having a printed circuit board is provided. In one embodiment, the printed circuit board includes a plurality of external pads to be coupled with an external device and a plurality of bypass pads for testing an electric circuit. The external pads are exposed and at least one of the plurality of bypass pads are not exposed from an outer surface of the PCB. A system using the electronic device and a method of testing an electronic device are also provided.

公开(公告)号：US08237276B2

公开(公告)日：2012-08-07

申请号：US12831256

申请日：2010-07-07

Applicant: Chi Jung Song ,  In Soo Kang ,  Gi Jo Jung ,  Yun Mook Park ,  Eung Ju Lee ,  Jun Kyu Lee ,  Jung Won Lee

Inventor： Chi Jung Song ,  In Soo Kang ,  Gi Jo Jung ,  Yun Mook Park ,  Eung Ju Lee ,  Jun Kyu Lee ,  Jung Won Lee

IPC: H01L23/48

CPC classification number: H01L24/13 ,  H01L23/13 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L24/93 ,  H01L2224/02126 ,  H01L2224/03462 ,  H01L2224/03464 ,  H01L2224/0347 ,  H01L2224/0348 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/056 ,  H01L2224/10126 ,  H01L2224/11462 ,  H01L2224/11474 ,  H01L2224/1148 ,  H01L2224/1181 ,  H01L2224/1182 ,  H01L2224/11848 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/11901 ,  H01L2224/13016 ,  H01L2224/13017 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16237 ,  H01L2224/81385 ,  H01L2224/814 ,  H01L2224/81815 ,  H01L2224/93 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01024 ,  H01L2924/01025 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3436 ,  H05K3/3478 ,  H05K2201/09472 ,  Y02P70/613 ,  H01L2924/00014 ,  H01L2224/11 ,  H01L2924/00 ,  H01L2224/1146

Abstract: There is provided a bump structure for a semiconductor device, comprising a metal post formed on and electrically connected to an electrode pad on a substrate, a solder post formed on the top surface of the metal post, said solder post having the same horizontal width as the metal post and the top surface of the solder post being substantially rounded, and an intermetallic compound layer disposed at the interface between the metal post and the solder post. An oxide layer formed on the solder post prevents solder post under reflow from being changed into a spherical shape. An intermetallic compound layer may be formed by an aging process at the interface between the metal post and the solder post. The bump structure can realize fine pitch semiconductor package without a short between neighboring bumps.

Abstract translation: 提供了一种用于半导体器件的凸块结构，包括形成在基板上的电极焊盘上并电连接到金属柱上的金属柱，形成在金属柱的顶表面上的焊料柱，所述焊料柱具有与 金属柱和焊料柱的顶表面基本上是圆形的，以及设置在金属柱和焊料柱之间的界面处的金属间化合物层。 形成在焊料柱上的氧化物层防止回流下的焊料柱变成球形。 可以通过在金属柱和焊料柱之间的界面处的老化过程形成金属间化合物层。 凸块结构可以实现精细的间距半导体封装，而不会在相邻凸块之间产生短路。

公开(公告)号：US08227710B2

公开(公告)日：2012-07-24

申请号：US11987255

申请日：2007-11-28

Applicant: Kenji Nagase ,  Kenichi Kawabata

Inventor： Kenji Nagase ,  Kenichi Kawabata

IPC: H05K1/11

CPC classification number: H05K3/4007 ,  H01L23/5389 ,  H01L24/24 ,  H01L24/82 ,  H01L2224/24051 ,  H01L2224/24226 ,  H01L2224/82039 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01037 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01047 ,  H01L2924/01057 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01088 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/30105 ,  H05K1/185 ,  H05K3/061 ,  H05K3/243 ,  H05K3/28 ,  H05K2201/0367 ,  H05K2201/09472 ,  H05K2201/09645 ,  H05K2201/10674 ,  H05K2203/054 ,  H05K2203/1152 ,  Y10T29/4913 ,  H01L2924/00

Abstract: Provided is a wiring structure and the like which can completely connect a wiring layer to a body to be wired while keeping insulation between two adjacent wiring layers and realize high density packaging due to a narrowed pitch.In a semiconductor-embedded substrate, a conductive pattern is formed on both sides of a core substrate and a semiconductor device is placed in a resin layer stacked over the core substrate. The resin layer has via-holes so that the conductive pattern and a bump of the semiconductor device protrude from the resin layer. Inside the via-holes, the bump and conductive pattern are respectively connected to via-hole electrode portions whose cross-sectional area has been increased toward the bottom of the via-hole. A void is defined between the via-hole electrode portion and upper portion of the inner wall of the via-hole.

Abstract translation: 本发明提供一种布线结构等，其可以在将布线层完全连接到待布线的本体上，同时保持两个相邻布线层之间的绝缘，并且由于间距变窄而实现高密度封装。 在半导体嵌入式基板中，在芯基板的两面形成导体图案，将半导体装置配置在层叠在芯基板上的树脂层中。 树脂层具有通孔，使得导电图案和半导体器件的凸块从树脂层突出。 在通孔内部，凸块和导电图案分别连接到横截面积已经朝向通孔底部增加的通孔电极部分。 在通孔电极部分和通孔的内壁的上部之间限定空隙。

公开(公告)号：US20120005886A1

公开(公告)日：2012-01-12

申请号：US13137756

申请日：2011-09-09

Applicant: Myung Sam Kang

Inventor： Myung Sam Kang

IPC: H05K3/00

CPC classification number: H05K1/111 ,  H01L2924/0002 ,  H05K3/205 ,  H05K3/28 ,  H05K3/3473 ,  H05K2201/0376 ,  H05K2201/09472 ,  H05K2201/09736 ,  Y02P70/611 ,  Y10T29/49124 ,  Y10T29/49126 ,  Y10T29/4913 ,  Y10T29/49147 ,  Y10T29/49149 ,  H01L2924/00

Abstract: A method of manufacturing a printed circuit board having a buried solder bump, including: preparing a carrier on which a circuit layer, a solder bump, and a circuit pattern formed on the solder bump are formed; pressing the carrier into an insulating layer so that the circuit layer, the solder bump and the circuit pattern are buried in the insulating layer; and removing the carrier.

Abstract translation: 一种制造具有埋置焊料凸块的印刷电路板的方法，包括：制备其上形成有电路层，焊料凸块和形成在焊料凸块上的电路图案的载体; 将载体压入绝缘层，使得电路层，焊料凸块和电路图案埋在绝缘层中; 并移除载体。

公开(公告)号：US20110281138A1

公开(公告)日：2011-11-17

申请号：US13144112

申请日：2010-01-26

Applicant: Shingo Yoshioka ,  Hiroaki Fujiwara

Inventor： Shingo Yoshioka ,  Hiroaki Fujiwara

IPC: G11B5/33 ,  H01L21/58 ,  H01L23/48 ,  H01L21/66

CPC classification number: H05K1/11 ,  G11B5/486 ,  H01L21/565 ,  H01L22/12 ,  H01L23/3121 ,  H01L24/03 ,  H01L24/05 ,  H01L24/24 ,  H01L24/25 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/82 ,  H01L24/83 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16237 ,  H01L2224/24011 ,  H01L2224/2405 ,  H01L2224/24051 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73267 ,  H01L2224/82009 ,  H01L2224/82039 ,  H01L2224/82101 ,  H01L2224/82931 ,  H01L2224/82947 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2224/92244 ,  H01L2225/06524 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01012 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01051 ,  H01L2924/01056 ,  H01L2924/01057 ,  H01L2924/01058 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/1461 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H05K1/111 ,  H05K1/117 ,  H05K1/181 ,  H05K3/184 ,  H05K2201/0376 ,  H05K2201/09472 ,  Y02P70/611 ,  Y10T428/1171 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207

Abstract: One aspect of the present invention is a method of mounting a semiconductor chip having: a step of forming a resin coating on a surface of a path connecting a bonding pad on a surface of a semiconductor chip and an electrode pad formed on a surface of an insulating base material; a step of forming, by laser beam machining, a wiring gutter having a depth that is equal to or greater than a thickness of the resin coating along the path for connecting the bonding pad and the electrode pad; a step of depositing a plating catalyst on a surface of the wiring gutter; a step of removing the resin coating; and a step of forming an electroless plating coating only at a site where the plating catalyst remains. Another aspect of the present invention is a three-dimensional structure in which a wiring is formed on a surface, wherein, on the surface of the three-dimensional structure, a recessed gutter for wiring is formed, extending between mutually intersecting adjacent faces of the three-dimensional structure, and wherein at least a part of a wiring conductor is embedded in the recessed gutter for wiring.

Abstract translation: 本发明的一个方面是一种安装半导体芯片的方法，该半导体芯片具有：在连接半导体芯片的表面上的接合焊盘的表面上形成树脂涂层的步骤和形成在半导体芯片的表面上的电极焊盘 绝缘基材; 通过激光束加工形成具有等于或大于沿着用于连接焊盘和电极焊盘的路径的树脂涂层的厚度的深度的布线槽的步骤; 将电镀催化剂沉积在布线槽的表面上的步骤; 去除树脂涂层的步骤; 以及仅在电镀催化剂保留的部位形成化学镀镀层的工序。 本发明的另一方面是其中在表面上形成布线的三维结构，其中在三维结构的表面上形成用于布线的凹槽，在相互相交的相邻面之间延伸 三维结构，并且其中布线导体的至少一部分嵌入到凹槽中用于布线。

公开(公告)号：US08047855B2

公开(公告)日：2011-11-01

申请号：US12693097

申请日：2010-01-25

Applicant: Gary Yasamura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram ,  Kevin P. Grundy

Inventor： Gary Yasamura ,  Joseph C. Fjelstad ,  William F. Wiedemann ,  Para K. Segaram ,  Kevin P. Grundy

IPC: H01R12/00 ,  H05K1/00

CPC classification number: H05K1/117 ,  H01R12/523 ,  H01R12/62 ,  H01R12/716 ,  H01R13/24 ,  H01R13/6587 ,  H05K1/142 ,  H05K3/366 ,  H05K3/368 ,  H05K2201/09063 ,  H05K2201/09445 ,  H05K2201/09472 ,  H05K2201/09709 ,  H05K2201/09845 ,  H05K2201/10189 ,  H05K2203/167

Abstract: An electrical connector comprised of a plurality of electrical contacts arranged in a stair-step configuration designed to mate with electrical components having electrical contacts arranged in a stair-step configuration. A direct connect signaling system comprised of stair-step electrical connectors mated to stair-step printed circuit boards, other stair-step electrical components, or combinations thereof.

Abstract translation: 一种电连接器，包括布置成阶梯式结构的多个电触点，其设计成与具有以阶梯状构造布置的电触点的电气部件配合。 一种直接连接信号系统，包括与台阶式印刷电路板，其他楼梯电气部件或其组合配合的楼梯级电连接器。