公开(公告)号：US20030188429A1

公开(公告)日：2003-10-09

申请号：US10435279

申请日：2003-05-08

Applicant: International Business Machines Corporation

Inventor： Takayuki Haze ,  Tsuneo Yabuuchi

IPC: H01K003/22 ,  H05K003/02

CPC classification number: H05K3/44 ,  H05K1/056 ,  H05K3/0023 ,  H05K3/0035 ,  H05K3/385 ,  H05K3/421 ,  H05K3/4644 ,  H05K2201/09509 ,  H05K2201/09554 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/086 ,  H05K2203/087 ,  H05K2203/1157 ,  Y10T29/49126 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49158 ,  Y10T29/49165

Abstract: The method for producing a printed wiring board comprising the steps of preparing a conductive substrate, forming an insulating layer on one surface of the said substrate, forming at least one via hole in the insulating layer, thermally curing the insulating layer, and reducing at least one oxidized layer formed on the other conductive surface of the substrate during the curing operation. Alternatively, the thermal cure may be accomplished in an atmosphere (e.g., reducing gas, inactive gas, or mixtures thereof) not conducive to oxide formation on metallized circuit surfaces.

Abstract translation: 一种制造印刷电路板的方法，包括以下步骤：制备导电基板，在所述基板的一个表面上形成绝缘层，在绝缘层中形成至少一个通孔，热固化绝缘层，并至少减少 在固化操作期间在基板的另一导电表面上形成一个氧化层。 或者，热固化可以在不利于金属化电路表面上的氧化物形成的气氛（例如还原气体，惰性气体或其混合物）中完成。

公开(公告)号：US20030166331A1

公开(公告)日：2003-09-04

申请号：US10248688

申请日：2003-02-10

Inventor： Ho-Ming Tong ,  Chun-Chi Lee ,  Jen-Kuang Fang ,  Min-Lung Huang ,  Jau-Shoung Chen ,  Ching-Huei Su ,  Chao-Fu Weng ,  Yung-Chi Lee ,  Yu-Chen Chou ,  Tsung-Hua Wu ,  Su Tao

IPC: H01L021/44

CPC classification number: H01L24/11 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05572 ,  H01L2224/1147 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/13099 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H05K3/3484 ,  H05K2201/09863 ,  H05K2203/043 ,  H05K2203/0568 ,  H05K2203/0594

Abstract: A bump fabrication process for forming a bump over a wafer having a plurality of bonding pads thereon is provided. A patterned solder mask layer having a plurality of openings that exposes the respective bonding pads is formed over a wafer. The area of the opening in a the cross-sectional area through a the bottom-section as well as through a the top-section of the opening is smaller than the area of the opening in a the cross-sectional area through a the mid-section of the opening. Solder material is deposited into the opening and then a reflow process is conducted fusing the solder material together to form a spherical bump inside the opening. Finally, the solder mask layer is removed. In addition, a pre-formed bump may form on the bonding pad of the wafer prior to forming the patterned solder mask layer over the wafer having at leastwith an opening that exposes the pre-formed bump. Solder material is deposited into the openings and then a reflow process is conducted fusing the solder material and the pre-formed bump together to form a spherical bump. The pre-formed bump and the solder material may be fabricated using different constituents.

Abstract translation: 提供了一种用于在其上具有多个接合焊盘的晶片上形成凸块的凸块制造工艺。 具有暴露各个接合焊盘的多个开口的图案化焊接掩模层形成在晶片上。 通过底部的横截面积中的开口面积以及通过开口的顶部的开口面积比通过中间部分的横截面积的开口面积小， 部分开幕。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料熔合在一起，以在开口内形成球形凸块。 最后，去除焊接掩模层。 此外，在晶片上形成图案化的焊料掩模层之前，至少具有暴露预形成的凸块的开口，可以在晶片的焊盘上形成预先形成的凸点。 将焊料沉积到开口中，然后进行回流工艺，将焊料材料和预形成的凸块熔合在一起形成球形凸块。 可以使用不同的成分制造预形成的凸块和焊料材料。

公开(公告)号：US20030150644A1

公开(公告)日：2003-08-14

申请号：US10367711

申请日：2003-02-19

Applicant: Ibiden Co., Ltd.

Inventor： Masaru Takada ,  Kiyotaka Tsukada ,  Hiroyuki Kobayashi ,  Hisashi Minoura ,  Yoshikazu Ukai ,  Mitsuhiro Kondo

IPC: H05K003/42

CPC classification number: H05K3/4652 ,  H01L21/486 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15153 ,  H01L2924/1517 ,  H05K1/0203 ,  H05K1/021 ,  H05K1/0271 ,  H05K1/0366 ,  H05K1/112 ,  H05K1/116 ,  H05K1/182 ,  H05K3/0035 ,  H05K3/0061 ,  H05K3/3468 ,  H05K3/3484 ,  H05K3/385 ,  H05K3/4038 ,  H05K3/421 ,  H05K3/423 ,  H05K3/427 ,  H05K3/428 ,  H05K3/429 ,  H05K3/4602 ,  H05K3/4611 ,  H05K2201/0305 ,  H05K2201/0394 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09518 ,  H05K2201/0969 ,  H05K2201/09781 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2203/0315 ,  H05K2203/041 ,  H05K2203/0554 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00014

Abstract: In production of a printed wiring board comprising innerlayer conductor circuits 161, 131 arranged among insulating layers 101null103 and blind via-holes 141, 142 formed from an outermost surface of the insulating layer toward the innerlayer conductor circuit, an opening hole 160 is previously formed in a central portion of the innerlayer conductor circuit 161 located at the bottom of the blind via-hole 141, and laser beams are irradiated from the outermost surface of the insulating layer to form the blind via-holes 141, 142. Thereafter, a metal plated film is formed on surfaces of the innerlayer conductor circuits 131, 161 and the blind via-holes 141, 142.

Abstract translation: 在制造印刷布线板时，包括布置在绝缘层101〜103之间的内层导体电路161,131和从绝缘层的最外表面向内层导体电路形成的盲通孔141,142，预先设置有开孔160 形成在位于盲孔通孔141的底部的内层导体电路161的中心部分，并且从绝缘层的最外表面照射激光束以形成盲通孔141,142。此后， 在内层导体电路131,161和盲通孔141,142的表面上形成金属电镀膜。

公开(公告)号：US20030102158A1

公开(公告)日：2003-06-05

申请号：US10281463

申请日：2002-10-25

Inventor： Miguel A. Jimarez ,  Ross W. Keesler ,  Voya R. Markovich ,  Rajinder S. Rai ,  Cheryl L. Tytran-Palomaki

IPC: H05K001/00 ,  H05K001/03

CPC classification number: H01L21/486 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/15311 ,  H05K1/112 ,  H05K3/28 ,  H05K3/3457 ,  H05K3/3484 ,  H05K3/429 ,  H05K3/4602 ,  H05K2201/09436 ,  H05K2201/09509 ,  H05K2201/09863 ,  H05K2203/043 ,  Y10T29/49155 ,  Y10T29/49165 ,  H01L2924/00

Abstract: A chip carrier structure and method for forming the same having a receptor pad formed therein. The structure comprises a circuitized substrate having a conductive element on the surface, an External Dielectric Layer mounted on the circuitized substrate with an opening positioned above the conductive element to form a microvia. The walls of the microvia are first treated to enhance copper adhesion and then are electroplated to provide a receptor pad. Finally, a solder paste is deposited within the microvia to create a solder deposit or bump.

公开(公告)号：US20020179335A1

公开(公告)日：2002-12-05

申请号：US10197125

申请日：2002-07-17

Applicant: International Business Machines Corporation

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H01R012/04 ,  H05K003/02

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 nullm-125 nullm) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

公开(公告)号：US06452117B2

公开(公告)日：2002-09-17

申请号：US09871555

申请日：2001-05-31

Applicant: Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

Inventor： Brian Eugene Curcio ,  Peter Alfred Gruber ,  Frederic Maurer ,  Konstantinos I. Papathomas ,  Mark David Poliks

IPC: H01R1204

CPC classification number: H05K3/4069 ,  H01L21/486 ,  H01L23/49827 ,  H01L23/49833 ,  H01L2924/0002 ,  H05K3/0094 ,  H05K3/246 ,  H05K3/4602 ,  H05K2201/0305 ,  H05K2201/0347 ,  H05K2201/09509 ,  H05K2201/09536 ,  H05K2201/0959 ,  H05K2201/096 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2203/0126 ,  H05K2203/085 ,  Y10T29/4913 ,  Y10T29/49155 ,  Y10T29/49165 ,  Y10T29/53191 ,  H01L2924/00

Abstract: High aspect ratio (5:1-30:1) and small (5 &mgr;m-125 &mgr;m) diameter holes in a dielectric substrate are provided, which are filled with a solidified conductive material, as well as a method of filling such holes using pressure and vacuum. In certain embodiments, the holes are lined with conductive material and/or capped with a conductive material. The invention also contemplates a chip carrier formed by such material.

Abstract translation: 提供介电基片中的高纵横比（5：1-30：1）和小（5毫米-125毫米）直径的孔，填充有凝固的导电材料，以及使用压力填充这些孔的方法 和真空。 在某些实施例中，孔用导电材料衬里和/或用导电材料封盖。 本发明还考虑由这种材料形成的芯片载体。

公开(公告)号：US4940181A

公开(公告)日：1990-07-10

申请号：US333670

申请日：1989-04-06

Applicant: Frank J. Juskey, Jr. ,  Barry M. Miles ,  Anthony B. Suppelsa

Inventor： Frank J. Juskey, Jr. ,  Barry M. Miles ,  Anthony B. Suppelsa

IPC: B23K1/20 ,  H05K1/11 ,  H05K3/34 ,  H05K3/46

CPC classification number: B23K1/203 ,  H05K1/111 ,  H05K1/112 ,  H05K3/3436 ,  B23K2201/40 ,  H01L2224/16237 ,  H05K2201/09036 ,  H05K2201/09472 ,  H05K2201/09509 ,  H05K2201/09745 ,  H05K2201/09827 ,  H05K2201/09863 ,  H05K2201/10734 ,  H05K2203/048 ,  H05K3/4644 ,  Y02P70/611 ,  Y02P70/613

Abstract: A pad grid array comprises an array of cavities (12) formed in a circuit carrying substrate (10) that are metallized (18, 20, and 22) to provide electrical conductivity. The metallized cavities are preferably hemispherical in shape and approximately the size of the solder bumps (30) coupled to a solder bumped chip carrier (28) that will be mounted thereon. Flux (26) is applied to each of the metallized cavities before positioning the solder bumped chip (28) carrier over the pad grid array. Proper mounting can be detected by tactile sensing in either human or robotic assemblers when the solder bumps "drop" into the metallized cavities.

Abstract translation: 垫栅格阵列包括形成在电路承载衬底（10）中的金属化（18,20和22）以提供导电性的空腔阵列（12）。 金属化腔体的形状优选为半球形，并且大致与焊接凸块（30）的尺寸相连接，其将被安装在其上的焊料凸起的芯片载体（28）上。 在将焊料凸起的芯片（28）载体定位在焊盘格栅阵列上之前，将焊剂（26）施加到每个金属化空腔。 当焊料凸起“掉入”到金属化空腔中时，可以通过人体或机器人组装器中的触觉感测来检测正确的安装。

公开(公告)号：US09877387B2

公开(公告)日：2018-01-23

申请号：US14779232

申请日：2014-03-26

Applicant: KYOCERA Corporation

Inventor： Satoshi Kajita ,  Mitsuhiro Hagihara ,  Yuuhei Matsumoto

IPC: H05K7/00 ,  H05K1/03 ,  H05K1/11 ,  H05K3/42 ,  H05K1/02 ,  H05K1/09 ,  H05K1/18 ,  H05K3/46 ,  H05K3/00

CPC classification number: H05K1/0306 ,  H05K1/0298 ,  H05K1/036 ,  H05K1/09 ,  H05K1/115 ,  H05K1/181 ,  H05K3/0038 ,  H05K3/421 ,  H05K3/4602 ,  H05K3/4655 ,  H05K2201/0116 ,  H05K2201/0195 ,  H05K2201/0209 ,  H05K2201/0266 ,  H05K2201/09845 ,  H05K2201/09854 ,  H05K2201/09863 ,  H05K2201/2072

Abstract: A wiring board includes: an inorganic insulating layer having a via hole formed so as to penetrate the inorganic insulating layer in a thickness direction thereof; a conductive layer disposed on the inorganic insulating layer; and a via conductor which adheres to an inner wall of the via hole and is connected with the conductive layer. The inorganic insulating layer includes a first section including a plurality of inorganic insulating particles partly connected to each other, and a resin portion located in gaps between the inorganic insulating particles, and a second section which is interposed between the first section and the via conductor, including a plurality of inorganic insulating particles partly connected to each other, and a conducting portion composed of part of the via conductor which is located in gaps between the inorganic insulating particles.

公开(公告)号：US09814139B2

公开(公告)日：2017-11-07

申请号：US15124499

申请日：2015-02-27

Applicant: Sony Corporation

Inventor： Toshihiko Watanabe

IPC: H05K1/16 ,  H05K1/11 ,  H05K3/34 ,  H01L23/498 ,  H01L21/48 ,  H05K3/00 ,  H05K3/40 ,  H05K3/42 ,  H05K1/03 ,  H01L33/48

CPC classification number: H05K1/116 ,  H01L21/486 ,  H01L23/49827 ,  H01L33/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2924/1531 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/0306 ,  H05K1/112 ,  H05K1/115 ,  H05K3/0094 ,  H05K3/3436 ,  H05K3/3447 ,  H05K3/3489 ,  H05K3/4007 ,  H05K3/42 ,  H05K2201/09154 ,  H05K2201/0959 ,  H05K2201/09863 ,  H05K2201/10106 ,  H05K2201/10484 ,  H05K2203/1383 ,  H05K2203/1394 ,  Y02P70/613

Abstract: A mounting substrate includes a through-hole 13 formed in a substrate 10, a first land part 21, a second land part 31, a first component attaching part 22, a second component attaching part 32, a conductive layer 14, and a filling member 15 filled into a part of the through-hole 13. A shortest distance allowable value L0 from the center of the first land part 21 to a component 51 is determined on the basis of the volume Vh of a part of the through-hole 15 positioned above a top surface of the filling member 15 on the side of the first land part 21, the length L1 of the component 51 to be mounted to the first component attaching part 22, and the maximum allowable value of the inclination of the component 51 to be mounted to the first component attaching part 22 relative to the first surface 11 of the substrate 10.

公开(公告)号：US09351081B2

公开(公告)日：2016-05-24

申请号：US13779210

申请日：2013-02-27

Applicant: Texas Instruments Incorporated

Inventor： Peter B Johnson ,  Ira Oaktree Wygant

IPC: H02N1/00 ,  H04R19/00 ,  B06B1/02

CPC classification number: B06B1/0292 ,  B06B2201/76 ,  B81B7/007 ,  B81B2203/0127 ,  B81B2207/096 ,  B81C1/00301 ,  B81C2201/013 ,  B81C2203/036 ,  H02N1/006 ,  H04R19/005 ,  H05K2201/09845 ,  H05K2201/09863

Abstract: A Capacitive Micromachined Ultrasonic Transducer (CMUT) device includes at least one CMUT cell including a first substrate of a single crystal material having a top side including a patterned dielectric layer thereon including a thick and a thin dielectric region, and a through-substrate via (TSV) extending a full thickness of the first substrate. The TSV is formed of the single crystal material, is electrically isolated by isolation regions in the single crystal material, and is positioned under a top side contact area of the first substrate. A membrane layer is bonded to the thick dielectric region and over the thin dielectric region to provide a movable membrane over a micro-electro-mechanical system (MEMS) cavity. A metal layer is over the top side substrate contact area and over the movable membrane including coupling of the top side substrate contact area to the movable membrane.

Abstract translation: 电容式微加工超声波传感器（CMUT）装置包括至少一个CMUT单元，其包括单晶材料的第一基板，其具有包括厚和薄的电介质区域的在其上的图案化电介质层的顶侧，以及贯穿基板通孔 TSV）延伸第一基板的整个厚度。 TSV由单晶材料形成，通过单晶材料中的隔离区电隔离，并且位于第一基板的顶侧接触区域的下方。 膜层结合到厚电介质区域和薄介电区域上，以在微机电系统（MEMS）腔体上提供可移动膜。 金属层在顶侧基板接触区域上方并且在可移动膜上方，包括顶侧基板接触区域与可动膜的耦合。