公开(公告)号：US09531209B2

公开(公告)日：2016-12-27

申请号：US14822478

申请日：2015-08-10

Applicant: International Business Machines Corporation

Inventor： Mark C. Lamorey ,  Janak G. Patel ,  Peter Slota, Jr. ,  David B. Stone

IPC: H01L21/44 ,  H02J7/00 ,  H01L23/64 ,  H01L23/552 ,  H01L23/50 ,  H01L23/498 ,  H01L23/36 ,  H01L23/367 ,  H01L25/16 ,  H01L25/065 ,  H02J7/34 ,  H01L23/00 ,  H01L25/18 ,  H05K1/02 ,  H05K1/14 ,  H05K1/16

CPC classification number: H01L23/552 ,  H01L23/36 ,  H01L23/367 ,  H01L23/3672 ,  H01L23/3675 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/50 ,  H01L23/642 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/165 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/0557 ,  H01L2224/06181 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/1624 ,  H01L2224/17181 ,  H01L2224/29011 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2224/81815 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06537 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/12042 ,  H01L2924/141 ,  H01L2924/1421 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/15151 ,  H01L2924/15311 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1659 ,  H01L2924/16747 ,  H02J7/0042 ,  H02J7/0052 ,  H02J7/345 ,  H05K1/0204 ,  H05K1/021 ,  H05K1/0215 ,  H05K1/0216 ,  H05K1/144 ,  H05K1/162 ,  H05K2201/0116 ,  H05K2201/0187 ,  H05K2201/041 ,  H05K2201/0999 ,  H05K2201/10515 ,  H05K2201/1056 ,  H01L2924/014 ,  H01L2924/00

Abstract: Package assemblies including a die stack and related methods of use. The package assembly includes a substrate with a first surface, a second surface, and a third surface bordering a through-hole extending from the first surface to the second surface. The assembly further includes a die stack, a conductive layer, and a lid. The die stack includes a chip positioned inside the through-hole in the substrate. A section of the conductive layer is disposed on the third surface of the substrate. A portion of the lid is disposed between the first chip and the section of the conductive layer. The conductive layer is configured to be coupled with power, and the lid is configured to be coupled with ground. The portion of the lid may act as a first plate of a capacitor, and the section of the conductive layer may act as a second plate of the capacitor.

公开(公告)号：US20160316565A1

公开(公告)日：2016-10-27

申请号：US14695057

申请日：2015-04-24

Applicant: Unimicron Technology Corp.

Inventor： Yin-Ju CHEN ,  Ming-Hao WU ,  Cheng-Po YU

IPC: H05K1/18 ,  H05K1/11 ,  H01L35/30 ,  H05K3/30 ,  H05K3/40 ,  H05K1/02 ,  H05K3/46

CPC classification number: H05K3/4647 ,  G06F1/206 ,  H01L23/12 ,  H01L23/13 ,  H01L23/4275 ,  H01L23/49827 ,  H01L35/30 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15153 ,  H01L2924/15313 ,  H05K1/0203 ,  H05K1/0206 ,  H05K1/113 ,  H05K1/14 ,  H05K1/181 ,  H05K1/185 ,  H05K1/187 ,  H05K3/36 ,  H05K3/4697 ,  H05K2201/048 ,  H05K2201/10219 ,  H05K2201/10378 ,  H05K2201/10515 ,  H05K2201/10734

Abstract: A circuit board with a heat-recovery function includes a substrate, a heat-storing device, and a thermoelectric device. The heat-storing device is embedded in the substrate and connected to a processor for performing heat exchange with the processor. The thermoelectric device embedded in the substrate includes a first metal-junction surface and a second metal-junction surface. The first metal-junction surface is connected to the heat-storing device for performing heat exchange with the heat-storing device. The second metal-junction surface is joined with the first metal-junction surface, in which the thermoelectric device generates an electric potential by a temperature difference between the first metal-junction surface and the second metal-junction surface.

公开(公告)号：US09480149B2

公开(公告)日：2016-10-25

申请号：US14230843

申请日：2014-03-31

Applicant: Brocade Communications Systems, Inc.

Inventor： Shahriar Mokhtarzad

IPC: H05K1/02 ,  H05K9/00 ,  H05K1/18

CPC classification number: H05K1/0272 ,  H05K1/0203 ,  H05K1/181 ,  H05K9/0024 ,  H05K2201/064 ,  H05K2201/09072 ,  H05K2201/10515 ,  H05K2201/10522

Abstract: An embodiment of an electronic system includes a printed circuit board (PCB) including fluid flow channel extending through the PCB. In addition, the electronic system includes an electronic component including a bottom surface and positioned on the PCB over the fluid flow channel to thereby expose the bottom surface of the electronic component to fluid flow through the fluid flow channel.

Abstract translation: 电子系统的实施例包括印刷电路板（PCB），其包括延伸穿过PCB的流体流动通道。 此外，电子系统包括电子部件，该电子部件包括底表面，并且位于流体流动通道上的PCB上，从而将电子部件的底部表面暴露于通过流体流动通道的流体流动。

公开(公告)号：US09451694B2

公开(公告)日：2016-09-20

申请号：US14663447

申请日：2015-03-19

Applicant: IBIS Innotech Inc.

Inventor： Chih-Kung Huang ,  Wei-Jen Lai ,  Wen-Chun Liu

IPC: H05K7/10 ,  H05K7/12 ,  H05K1/03 ,  H05K3/18 ,  H05K3/40 ,  H05K3/46 ,  H05K1/11 ,  H05K3/00 ,  H05K3/10

CPC classification number: H05K1/0373 ,  H01L21/568 ,  H01L24/13 ,  H01L24/16 ,  H01L24/19 ,  H01L24/20 ,  H01L24/48 ,  H01L25/04 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/131 ,  H01L2224/16238 ,  H01L2224/16245 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/9222 ,  H01L2224/96 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/16195 ,  H01L2924/1715 ,  H01L2924/1815 ,  H01L2924/18162 ,  H01L2924/19105 ,  H05K1/113 ,  H05K3/0014 ,  H05K3/105 ,  H05K3/188 ,  H05K3/4007 ,  H05K3/4697 ,  H05K2201/0236 ,  H05K2201/0376 ,  H05K2201/09063 ,  H05K2201/09118 ,  H05K2201/0919 ,  H05K2201/10151 ,  H05K2201/10515 ,  H05K2201/10674 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/014

Abstract: A package structure includes a selective-electroplating epoxy compound, a first patterned circuit layer, second patterned circuit layers, metal studs, contact pads and conductive vias. The selective-electroplating epoxy compound includes cavities, a first surface and a second surface. The cavities disposed on the first surface in array arrangement. The selective-electroplating epoxy compound is formed by combining non-conductive metal complex. The metal studs are disposed in the cavities respectively and protruded from the first surface. The first patterned circuit layer is directly disposed on the first surface. The selective-electroplating epoxy compound exposes a top surface of the patterned circuit layer. The top surface is lower than or coplanar with the first surface. The second patterned circuit layers are directly disposed on the second surface. The conductive vias are disposed at the selective-electroplating epoxy compound to electrically connect the second patterned circuit layers to the corresponding metal studs.

Abstract translation: 封装结构包括选择性电镀环氧化合物，第一图案化电路层，第二图案化电路层，金属柱，接触焊盘和导电通孔。 选择性电镀环氧化合物包括空腔，第一表面和第二表面。 排列在第一表面上的空腔。 选择性电镀环氧化合物通过组合非导电金属络合物形成。 金属螺柱分别设置在空腔中并从第一表面突出。 第一图案化电路层直接设置在第一表面上。 选择性电镀环氧化合物暴露图案化电路层的顶表面。 顶面低于或与第一表面共面。 第二图案化电路层直接设置在第二表面上。 导电通孔设置在选择性电镀环氧化合物处，以将第二图案化电路层电连接到相应的金属螺柱。

公开(公告)号：US09437582B2

公开(公告)日：2016-09-06

申请号：US14257795

申请日：2014-04-21

Applicant: Tessera, Inc.

Inventor： David Gibson ,  Andy Stavros

IPC: H01L25/10 ,  H05K1/11 ,  H01L23/498 ,  H01L23/00 ,  H05K1/14 ,  H05K3/34 ,  H01L25/065

CPC classification number: H01L25/10 ,  H01L23/49816 ,  H01L23/49833 ,  H01L23/4985 ,  H01L24/14 ,  H01L24/17 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2225/0652 ,  H01L2225/06527 ,  H01L2225/06548 ,  H01L2225/06572 ,  H01L2225/1023 ,  H01L2225/107 ,  H01L2924/1437 ,  H01L2924/15311 ,  H05K1/112 ,  H05K1/141 ,  H05K3/3436 ,  H05K2201/10378 ,  H05K2201/10515 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: A microelectronic assembly includes units superposed on one another to form at least one stack having a vertical direction. Each unit includes one or more microelectronic devices and has top and bottom surfaces. Top unit terminals are exposed at the top surfaces and bottom unit terminals are exposed at the bottom surfaces. The top and bottom unit terminals are provided at a set of ordered column positions. Each top unit terminal of the set, except the top unit terminals at the highest ordered column position, is connected to a respective bottom unit terminal of the same unit at a next higher ordered column position. Each bottom unit terminal of the set, except the bottom unit terminals of the lowest unit in the stack, is connected to a respective upper unit terminal of the next lower unit in the stack at the same column position.

Abstract translation: 微电子组件包括彼此叠置以形成具有垂直方向的至少一个堆叠的单元。 每个单元包括一个或多个微电子器件，并且具有顶表面和底表面。 顶部单元端子在顶部表面露出，底部单元端子暴露在底部表面。 顶部和底部单元端子设置在一组有序列位置。 除了在最高有序列位置的顶部单元端子之外，组件的每个顶部单元端子在下一个更高排序的列位置处连接到同一单元的相应底部单元端子。 除了堆叠中最低单元的底部单元端子之外，组件的每个底部单元端子连接到堆叠中的下一个下部单元的相应上部单元端子处于相同的列位置。

公开(公告)号：US20160163613A1

公开(公告)日：2016-06-09

申请号：US14900651

申请日：2014-06-24

Applicant: DENSO CORPORATION

Inventor： Shinya UCHIBORI ,  Norihisa IMAIZUMI ,  Masayuki TAKENAKA

IPC: H01L23/31 ,  H05K1/18 ,  H01L23/498

CPC classification number: H01L23/3157 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49827 ,  H01L24/73 ,  H01L25/16 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H05K1/181 ,  H05K3/284 ,  H05K3/301 ,  H05K3/3415 ,  H05K2201/09436 ,  H05K2201/10462 ,  H05K2201/10515 ,  H05K2201/10537 ,  H05K2201/10583 ,  H05K2201/10757 ,  H05K2201/2036 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An electronic apparatus includes a board, a first electronic component, a mold resin and a second electronic component. The board has a first surface and a second surface opposite to the first surface. The first electronic component is mounted on the first surface of the board. The mold resin seals the first electronic component and the first surface of the board. The second electronic component is arranged on the mold resin.

Abstract translation: 电子设备包括板，第一电子部件，模具树脂和第二电子部件。 板具有与第一表面相对的第一表面和第二表面。 第一电子部件安装在板的第一表面上。 模具树脂密封第一电子部件和板的第一表面。 第二电子部件布置在模制树脂上。

公开(公告)号：US09341773B2

公开(公告)日：2016-05-17

申请号：US14280648

申请日：2014-05-18

Applicant: Achyut Kumar Dutta

Inventor： Achyut Kumar Dutta

IPC: H01L27/02 ,  G02B6/12 ,  G02B6/122 ,  G02B6/42 ,  G02B6/43 ,  H05K1/02 ,  H05K1/14 ,  H05K1/18

CPC classification number: G02B6/12002 ,  G02B6/122 ,  G02B6/32 ,  G02B6/4214 ,  G02B6/4224 ,  G02B6/4257 ,  G02B6/4268 ,  G02B6/4279 ,  G02B6/428 ,  G02B6/43 ,  G02B2006/12147 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L25/167 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2224/16238 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/09701 ,  H01L2924/10329 ,  H01L2924/10335 ,  H01L2924/12042 ,  H01L2924/12043 ,  H01L2924/1432 ,  H01L2924/1434 ,  H01L2924/1461 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01S5/02248 ,  H01S5/02272 ,  H01S5/183 ,  H05K1/0274 ,  H05K1/141 ,  H05K1/144 ,  H05K1/181 ,  H05K2201/10121 ,  H05K2201/10515 ,  H05K2201/10734 ,  Y02P70/611 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/45099

Abstract: An optoelectronics chip-to-chip interconnects system is provided, including at least one packaged chip to be connected on the printed-circuit-board with at least one other packaged chip, optical-electrical (O-E) conversion mean, waveguide-board, and (PCB). Single to multiple chips interconnects can be interconnected provided using the technique disclosed in this invention. The packaged chip includes semiconductor die and its package based on the ball-grid array or chip-scale-package. The O-E board includes the optoelectronics components and multiple electrical contacts on both sides of the O-E substrate. The waveguide board includes the electrical conductor transferring the signal from O-E board to PCB and the flex optical waveguide easily stackable onto the PCB to guide optical signal from one chip-to-other chip. Alternatively, the electrode can be directly connected to the PCB instead of including in the waveguide board. The chip-to-chip interconnections system is pin-free and compatible with the PCB. The main advantages of this invention are to use the packaged chip for interconnection and the conventional PCB technology can be used for low speed electrical signal connection. Also, the part of the heat from the packaged chip can be transmitted to the PCB through the conductors, so that complex cooling system can be avoided.

Abstract translation: 提供了一种光电子芯片到芯片互连系统，包括至少一个要连接在印刷电路板上的封装芯片与至少一个其它封装芯片，光电（OE）转换平均值，波导板和 （PCB）。 可以使用本发明公开的技术将单芯片至多片芯片互连互连。 封装芯片包括基于球栅阵列或芯片级封装的半导体管芯及其封装。 O-E板包括O-E基板两侧的光电子元件和多个电触点。 波导板包括将信号从O-E板传输到PCB的电导体，并且柔性光波导容易地堆叠到PCB上以引导来自一个芯片到另一个芯片的光信号。 或者，电极可以直接连接到PCB，而不是包括在波导板中。 芯片到芯片互连系统是无引脚的，与PCB兼容。 本发明的主要优点是使用封装芯片进行互连，并且传统的PCB技术可用于低速电信号连接。 此外，来自封装芯片的部分热量可以通过导体传输到PCB，从而可以避免复杂的冷却系统。

公开(公告)号：US20160066428A1

公开(公告)日：2016-03-03

申请号：US14939102

申请日：2015-11-12

Applicant: Murata Manufacturing Co., Ltd.

Inventor： Shigeru Tago ,  Yuki Wakabayashi ,  Hirofumi Shinagawa

IPC: H05K1/18 ,  H05K1/11 ,  H05K1/03 ,  H05K1/02

CPC classification number: H05K1/185 ,  H01L23/5389 ,  H01L24/19 ,  H01L2224/04105 ,  H05K1/0298 ,  H05K1/0313 ,  H05K1/11 ,  H05K1/186 ,  H05K3/4617 ,  H05K3/4632 ,  H05K2201/0141 ,  H05K2201/0154 ,  H05K2201/10515

Abstract: A component-embedded substrate includes a first embedded component positioned in a layer close to a mounting electrode and a second embedded component positioned in a layer farther away from the mounting electrode than the first embedded component. The first and second embedded components include electrically connected terminals. Each resin film of the substrate is formed of thermoplastic resin. The first embedded component has more terminals than the second embedded component. Many of the internal wires from the first and second embedded component extend towards a mounting surface where the mounting electrode is provided. However, since in plan view the area of the first embedded component is smaller than the second embedded component, and the first embedded component is disposed closer to the mounting surface than the second embedded component, there is space for routing the internal wires at the side of the mounting surface of the substrate.

Abstract translation: 组件嵌入式基板包括位于靠近安装电极的层中的第一嵌入式部件和位于比第一嵌入式部件更远离安装电极的层中的第二嵌入式部件。 第一和第二嵌入式部件包括电连接端子。 基板的各树脂膜由热塑性树脂形成。 第一个嵌入式组件具有比第二个嵌入式组件更多的端子。 来自第一和第二嵌入式部件的许多内部电线朝向设置有安装电极的安装表面延伸。 然而，由于在平面图中，第一嵌入式部件的面积小于第二嵌入式部件，所以第一嵌入部件配置成比第二嵌入部件更靠近安装面，因此存在用于在侧面布线内部电线的空间 的基板的安装表面。

公开(公告)号：US20160050748A1

公开(公告)日：2016-02-18

申请号：US14779961

申请日：2014-03-20

Applicant: PS4 LUXCO S.A.R.L.

Inventor： Sensho Usami

IPC: H05K1/02 ,  H05K1/18

CPC classification number: H05K1/0271 ,  H01L21/561 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/06135 ,  H01L2224/2919 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2224/85207 ,  H01L2224/8592 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3511 ,  H05K1/181 ,  H05K2201/10515 ,  H05K2201/2009 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00014

Abstract: One semiconductor device includes a wiring substrate, a first semiconductor chip that is mounted on one surface of the wiring substrate, a second semiconductor chip that is laminated on the first semiconductor chip so as to form exposed surfaces where the surface of the first semiconductor chip is partially exposed, silicon substrates that are mounted on the exposed surfaces and serve as warping control members, and an encapsulation body that is formed on the wiring substrate so as to cover the first semiconductor chip, the second semiconductor chip and the silicon substrates.

Abstract translation: 一个半导体器件包括布线基板，安装在布线基板的一个表面上的第一半导体芯片，层叠在第一半导体芯片上以形成第一半导体芯片的表面的暴露表面的第二半导体芯片 部分露出的硅基板，其安装在暴露的表面上并用作翘曲控制构件;以及封装体，其形成在布线基板上以覆盖第一半导体芯片，第二半导体芯片和硅基板。

公开(公告)号：US20160027715A1

公开(公告)日：2016-01-28

申请号：US14803889

申请日：2015-07-20

Applicant: J-DEVICES CORPORATION

Inventor： Shinji WATANABE ,  Sumikazu HOSOYAMADA ,  Shingo NAKAMURA ,  Hiroshi DEMACHI ,  Takeshi MIYAKOSHI ,  Tomoshige CHIKAI ,  Kiminori ISHIDO ,  Hiroaki MATSUBARA ,  Takashi NAKAMURA ,  Hirokazu HONDA ,  Yoshikazu KUMAGAYA ,  Shotaro SAKUMOTO ,  Toshihiro IWASAKI ,  Michiaki TAMAKAWA

IPC: H01L23/373 ,  H05K1/18 ,  H01L23/31 ,  H05K1/02 ,  H01L25/065 ,  H01L23/367

CPC classification number: H05K1/181 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L23/3733 ,  H01L23/4334 ,  H01L23/49816 ,  H01L25/105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1094 ,  H01L2924/15331 ,  H01L2924/1815 ,  H05K1/0204 ,  H05K1/0206 ,  H05K1/0209 ,  H05K1/141 ,  H05K2201/0275 ,  H05K2201/066 ,  H05K2201/10515 ,  H05K2203/1311 ,  H05K2203/1322 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A stacked semiconductor package includes a first semiconductor package including a first circuit board and a first semiconductor device mounted on the first circuit board; a second semiconductor package including a second circuit board and a second semiconductor device mounted on the second circuit board, the second semiconductor package being stacked on the first semiconductor package; and a heat transfer member provided on the first semiconductor device and a part of the first circuit board, the part being around the first semiconductor device.

Abstract translation: 叠层半导体封装包括：第一半导体封装，包括第一电路板和安装在第一电路板上的第一半导体器件; 第二半导体封装，包括第二电路板和安装在第二电路板上的第二半导体器件，第二半导体封装堆叠在第一半导体封装上; 以及设置在第一半导体器件上的传热部件和第一电路板的一部分，该部分围绕第一半导体器件。